From 92f4761198d24fb73cbe5bcd12b0ebf5bb766b4d Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Fri, 2 Mar 2018 13:37:59 +0100 Subject: intel/compiler: split float to 64-bit opcodes from int to 64-bit Going forward having these split is a bit more convenient since these two groups have different restrictions. v2: - Rebased on top of new regioning lowering pass. Reviewed-by: Topi Pohjolainen (v1) Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index fb35ff5ccbd..5add83b257d 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -907,10 +907,17 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_f2f64: case nir_op_f2i64: case nir_op_f2u64: + assert(type_sz(op[0].type) > 2); /* brw_nir_lower_conversions */ + inst = bld.MOV(result, op[0]); + inst->saturate = instr->dest.saturate; + break; + case nir_op_i2f64: case nir_op_i2i64: case nir_op_u2f64: case nir_op_u2u64: + assert(type_sz(op[0].type) > 1); /* brw_nir_lower_conversions */ + /* fallthrough */ case nir_op_f2f32: case nir_op_f2i32: case nir_op_f2u32: -- cgit v1.2.3