From 71a86d1fc69a025754d8d4c21f5777b21c65a3ea Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 16 May 2018 17:33:17 -0700 Subject: intel/fs: Use groups for SIMD16 LINTERP on gen11+ This is better than compression control because it naturally extends to SIMD32. v2: - Push/pop instruction state around adjusted codegen (Ken) Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner --- src/intel/compiler/brw_fs_generator.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 0c050a73b4c..20e356e23e8 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -781,6 +781,7 @@ fs_generator::generate_linterp(fs_inst *inst, struct brw_reg dwQ = suboffset(interp, 1); struct brw_reg dwR = suboffset(interp, 3); + brw_push_insn_state(p); brw_set_default_exec_size(p, BRW_EXECUTE_8); if (inst->exec_size == 8) { @@ -795,16 +796,14 @@ fs_generator::generate_linterp(fs_inst *inst, */ brw_inst_set_saturate(p->devinfo, i[0], false); } else { - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); + brw_set_default_group(p, inst->group); i[0] = brw_MAD(p, acc, dwR, offset(delta_x, 0), dwP); i[1] = brw_MAD(p, offset(dst, 0), acc, offset(delta_x, 1), dwQ); - brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF); + brw_set_default_group(p, inst->group + 8); i[2] = brw_MAD(p, acc, dwR, offset(delta_y, 0), dwP); i[3] = brw_MAD(p, offset(dst, 1), acc, offset(delta_y, 1), dwQ); - brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED); - brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod); brw_inst_set_cond_modifier(p->devinfo, i[3], inst->conditional_mod); @@ -816,6 +815,8 @@ fs_generator::generate_linterp(fs_inst *inst, brw_inst_set_saturate(p->devinfo, i[2], false); } + brw_pop_insn_state(p); + return true; } else if (devinfo->has_pln) { /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane": -- cgit v1.2.3