From 65c2362e88578575899bd208713d87b1206ad360 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Tue, 4 Feb 2020 10:49:59 -0800 Subject: iris: Use modfiy disables for 3DSTATE_WM_DEPTH_STENCIL command Add new IRIS_DIRTY_STENCIL_REF dirty flag which would help us to trigger separate 3DSTATE_WM_DEPTH_STENCIL packet using modify disable fields. Instead of merging two packets into one in order to build 3DSTATE_WM_DEPTH_STENCIL state, set_stencil_ref can use IRIS_DIRTY_STENCIL_REF bit and bind_zsa_state can use IRIS_DIRTY_WN_DEPTH_STENCIL, both could cause packet to happen with available information using modify disable bits which allow us to construct packet by ignoring set of fields. v2: (Kenneth Graunke) - Fix condition ordering. - Club GEN cases. Signed-off-by: Sagar Ghuge Reviewed-by: Kenneth Graunke Part-of: --- src/gallium/drivers/iris/iris_context.h | 1 + src/gallium/drivers/iris/iris_state.c | 35 +++++++++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 4acf2390e2f..9d681a5826e 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -139,6 +139,7 @@ enum { #define IRIS_DIRTY_PMA_FIX (1ull << 58) #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 59) #define IRIS_DIRTY_RENDER_BUFFER (1ull << 60) +#define IRIS_DIRTY_STENCIL_REF (1ull << 61) #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \ IRIS_DIRTY_SAMPLER_STATES_CS | \ diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 284d9d69e77..136297fd197 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1361,6 +1361,9 @@ iris_create_zsa_state(struct pipe_context *ctx, wmds.BackfaceStencilTestMask = state->stencil[1].valuemask; wmds.BackfaceStencilWriteMask = state->stencil[1].writemask; /* wmds.[Backface]StencilReferenceValue are merged later */ +#if GEN_GEN >= 12 + wmds.StencilReferenceValueModifyDisable = true; +#endif } #if GEN_GEN >= 12 @@ -2936,10 +2939,12 @@ iris_set_stencil_ref(struct pipe_context *ctx, { struct iris_context *ice = (struct iris_context *) ctx; memcpy(&ice->state.stencil_ref, state, sizeof(*state)); - if (GEN_GEN == 8) - ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE; - else + if (GEN_GEN >= 12) + ice->state.dirty |= IRIS_DIRTY_STENCIL_REF; + else if (GEN_GEN >= 9) ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL; + else + ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE; } static float @@ -5880,7 +5885,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) { struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa; -#if GEN_GEN >= 9 +#if GEN_GEN >= 9 && GEN_GEN < 12 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref; uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) { @@ -5889,6 +5894,9 @@ iris_upload_dirty_render_state(struct iris_context *ice, } iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds)); #else + /* Use modify disable fields which allow us to emit packets + * directly instead of merging them later. + */ iris_batch_emit(batch, cso->wmds, sizeof(cso->wmds)); #endif @@ -5897,6 +5905,25 @@ iris_upload_dirty_render_state(struct iris_context *ice, #endif } + if (dirty & IRIS_DIRTY_STENCIL_REF) { +#if GEN_GEN >= 12 + /* Use modify disable fields which allow us to emit packets + * directly instead of merging them later. + */ + struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref; + uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; + iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) { + wmds.StencilReferenceValue = p_stencil_refs->ref_value[0]; + wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1]; + wmds.StencilTestMaskModifyDisable = true; + wmds.StencilWriteMaskModifyDisable = true; + wmds.StencilStateModifyDisable = true; + wmds.DepthStateModifyDisable = true; + } + iris_batch_emit(batch, stencil_refs, sizeof(stencil_refs)); +#endif + } + if (dirty & IRIS_DIRTY_SCISSOR_RECT) { uint32_t scissor_offset = emit_state(batch, ice->state.dynamic_uploader, -- cgit v1.2.3