From 420627e6e79fe96504bbef463433bb827e597d84 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Dec 2017 09:20:21 +1000 Subject: radv/gfx9: fix buffer to image for 3d images on compute queues This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_meta_bufimage.c | 62 ++++++++++++++++++++++++++++--------- src/amd/vulkan/radv_private.h | 1 + 2 files changed, 48 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 1696f85ac16..5bcc1e62dba 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -259,19 +259,20 @@ radv_device_finish_meta_itob_state(struct radv_device *device) } static nir_shader * -build_nir_btoi_compute_shader(struct radv_device *dev) +build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d) { nir_builder b; + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D; const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT); - const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + const struct glsl_type *img_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "meta_btoi_cs"); + b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs"); b.shader->info.cs.local_size[0] = 16; b.shader->info.cs.local_size[1] = 16; b.shader->info.cs.local_size[2] = 1; @@ -296,16 +297,16 @@ build_nir_btoi_compute_shader(struct radv_device *dev) nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(offset, 0); - nir_intrinsic_set_range(offset, 12); + nir_intrinsic_set_range(offset, 16); offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); - offset->num_components = 2; - nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset"); + offset->num_components = is_3d ? 3 : 2; + nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset"); nir_builder_instr_insert(&b, &offset->instr); nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(stride, 0); - nir_intrinsic_set_range(stride, 12); - stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8)); + nir_intrinsic_set_range(stride, 16); + stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12)); stride->num_components = 1; nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride"); nir_builder_instr_insert(&b, &stride->instr); @@ -353,9 +354,10 @@ radv_device_init_meta_btoi_state(struct radv_device *device) { VkResult result; struct radv_shader_module cs = { .nir = NULL }; - - cs.nir = build_nir_btoi_compute_shader(device); - + struct radv_shader_module cs_3d = { .nir = NULL }; + cs.nir = build_nir_btoi_compute_shader(device, false); + if (device->physical_device->rad_info.chip_class >= GFX9) + cs_3d.nir = build_nir_btoi_compute_shader(device, true); /* * two descriptors one for the image being sampled * one for the buffer being written. @@ -395,7 +397,7 @@ radv_device_init_meta_btoi_state(struct radv_device *device) .setLayoutCount = 1, .pSetLayouts = &device->meta_state.btoi.img_ds_layout, .pushConstantRangeCount = 1, - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 12}, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16}, }; result = radv_CreatePipelineLayout(radv_device_to_handle(device), @@ -429,9 +431,33 @@ radv_device_init_meta_btoi_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail; + if (device->physical_device->rad_info.chip_class >= GFX9) { + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs_3d), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info_3d = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage_3d, + .flags = 0, + .layout = device->meta_state.btoi.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info_3d, NULL, + &device->meta_state.btoi.pipeline_3d); + ralloc_free(cs_3d.nir); + } ralloc_free(cs.nir); + return VK_SUCCESS; fail: + ralloc_free(cs_3d.nir); ralloc_free(cs.nir); return result; } @@ -448,6 +474,8 @@ radv_device_finish_meta_btoi_state(struct radv_device *device) &state->alloc); radv_DestroyPipeline(radv_device_to_handle(device), state->btoi.pipeline, &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->btoi.pipeline_3d, &state->alloc); } static nir_shader * @@ -1070,18 +1098,22 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, create_iview(cmd_buffer, dst, &dst_view); btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view); + if (device->physical_device->rad_info.chip_class >= GFX9 && + dst->image->type == VK_IMAGE_TYPE_3D) + pipeline = cmd_buffer->device->meta_state.btoi.pipeline_3d; radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); for (unsigned r = 0; r < num_rects; ++r) { - unsigned push_constants[3] = { + unsigned push_constants[4] = { rects[r].dst_x, rects[r].dst_y, - src->pitch + dst->layer, + src->pitch, }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 05ad480c578..a6959bfc0ae 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -438,6 +438,7 @@ struct radv_meta_state { VkPipelineLayout img_p_layout; VkDescriptorSetLayout img_ds_layout; VkPipeline pipeline; + VkPipeline pipeline_3d; } btoi; struct { VkPipelineLayout img_p_layout; -- cgit v1.2.3