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* glx: Fix glXGetFBConfigFromVisualSGIX.Stéphane Marchesin2011-05-271-1/+1
| | | | | | | | | | We want to check for Success, otherwise it will fail even with the right visual. NOTE: This is a candidate for the 7.10 branch. Signed-off-by: Antoine Labour <[email protected]> Signed-off-by: Stéphane Marchesin <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* mesa: set parameter list StateFlags field in _mesa_layout_parameters()Pierre-Eric Pelloux-Prayer2011-05-271-0/+1
| | | | | | | | | | | | When using _mesa_layout_parameters, all params copied in the 'layout' output in the PASS 1 don't modify StateFlags (because they are simply memcpy'ed). This patch fixes the problem, assuring output gl_prog_param_list StateFlags field is the same as the input one. NOTE: This is a candidate for the 7.10 branch. Signed-off-by: Brian Paul <[email protected]>
* i965/fs: Fix up for 8752764076e5b3f052a57e0134424a37bf2e9164.Eric Anholt2011-05-272-4/+4
| | | | I failed to commit and squash before pushing.
* mesa: Include shader target in dumps of GLSL source.Eric Anholt2011-05-271-1/+2
| | | | | | This makes automatic parsing of MESA_GLSL=dump output easier. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Do a FS compile up front at link time to produce link errors.Eric Anholt2011-05-275-27/+142
| | | | | | At glLinkShaders time, a fail() call in FS compile in 8-wide (the one that's required to succeed, though we may relax that at some point for pre-Ironlake performance) will now report out as a link error.
* i965/fs: Split the GLSL IR -> FS LIR visitor to brw_fs_visitor.cpp.Eric Anholt2011-05-274-1679/+1736
| | | | | | | | | We now have: brw_fs.cpp handles calling out to everything and optimization. brw_fs_visitor.cpp handles translating to our LIR. brw_fs_emit.cpp handles emitting from our LIR to native code. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Split the BRW native code emit to brw_fs_emit.cppEric Anholt2011-05-273-839/+876
| | | | | | | This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move a couple of GLSL IR -> BRW helper functions to brw_shader.cpp.Eric Anholt2011-05-273-49/+76
| | | | | | These will be used by the VS backend as well. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move non-FS-specific shader support to brw_shader.cpp.Eric Anholt2011-05-273-100/+129
| | | | | | | These only existed in brw_fs.cpp because it was the only .cpp file in the area when I wrote them. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Avoid generating MOVs for assignments of expressions.Eric Anholt2011-05-272-12/+75
| | | | | | No statistically significant difference measured in 3dbenchmark egypt/pro. It does reduce fragment shader instructions across shader-db by 0.3%.
* i965/fs: Move the computation of register block count from unit to compile.Eric Anholt2011-05-274-7/+18
| | | | | | | No net code size change, but unit update is down 0.8% code size pre-gen6. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Track fixed GRF regs separate from allocated GRF file in scheduling.Eric Anholt2011-05-272-1/+22
| | | | | | | | | | | | | | There's an assumption here that fixed GRFs will never intersect with the allocated GRFs. That's true today, though it might change some day if we decide to register-allocate the regs containing push constants once they're dead. This fixes a regression in 0f7325b89038937bd428f7c89ed9859189a0ab0b in Lightsmark from the texture instructions now containing g0 references instead of having that be implied. Performance is improved 15.2% +/- 3.6% (n=3). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34968
* i965/fs: Add a helper function for add_dep(before, after, before->latency).Eric Anholt2011-05-271-31/+19
| | | | | | This lets us avoid a bunch of before==NULL checks in the callers. Reviewed-by: Kenneth Graunke <[email protected]>
* nv50: fix emit_add_a16 to emit correct source regTrevor Davenport2011-05-271-2/+2
| | | | | | | | | | | emit_add_a16 was using the incorrect source. This caused adds in the form of: add u16 $a0 s32 $a1 u32 0x00000200 to have a source AREG of $a0 instead of $a1. Fixes World of Warcraft in OpenGL and D3D without GLSL.
* mesa: s/height/depth/ in texsubimage()Brian Paul2011-05-261-1/+1
| | | | Fixes http://bugs.freedesktop.org/show_bug.cgi?id=37648
* mesa: plug _mesa_GetObjectParameterivAPPLE into display list dispatch tableBrian Paul2011-05-261-0/+1
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* mesa: plug in GL_ARB_vertex_array_object display list functionsBrian Paul2011-05-261-0/+4
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* mesa: more geometry shader display list functionsBrian Paul2011-05-261-0/+53
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* mesa: more transform feedback display list functionsBrian Paul2011-05-261-12/+98
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* mesa: make query object API functions staticBrian Paul2011-05-262-24/+6
| | | | Only directly referenced by the _mesa_init_queryobj_dispatch() function.
* mesa: simplify query object display list dispatch setupBrian Paul2011-05-261-6/+2
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* i965: Pack the lookup and line_aa bits into the first dword of the key.Eric Anholt2011-05-261-2/+2
| | | | | | | They were occupying whole 32-bit words, despite being only 10 or so bits. Reduces code size slightly (80/3300 bytes). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove dead shadowtex_mask entry in the WM key.Eric Anholt2011-05-262-4/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.Eric Anholt2011-05-267-30/+10
| | | | | | | | | | From the GL 2.1 spec: "Required perspective-correct interpolation for all fragment attributes except depth in sections 3.4.1 and 3.5.1, effectively making GL PERSPECTIVE CORRECT HINT a no-op." Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Drop doubly irrelevant code in intelReadBuffers.Eric Anholt2011-05-261-12/+0
| | | | | | | | First, FBO read/draw == NULL validation happens in mesa core not intelReadBuffers -> intel_draw_buffers. Second, that condition is no longer tested for in our driver since ARB_ES2_compatibility was added. Reviewed-by: Brian Paul <[email protected]>
* mesa: Flush vertices before updating drawbuffer computed state.Eric Anholt2011-05-261-7/+7
| | | | | | | Otherwise, the driver is likely to draw the flushed vertices to the new drawbuffer instead of the old one, missing the point of the flush. Reviewed-by: Brian Paul <[email protected]>
* mesa: Allow NULL read/draw in complete FBOs in ARB_ES2_compatibility.Eric Anholt2011-05-261-1/+1
| | | | | | | | | | | | | | From the ARB_ES2_compatibility spec: "(8) How should we handle draw buffer completeness? RESOLVED: Remove draw/readbuffer completeness checks, and treat drawbuffers referring to missing attachments as if they were NONE." Fixes arb_es2_compatibility-drawbuffers when the short-circuit for ARB_ES2_compatibility in the previous commit is dropped. Reviewed-by: Brian Paul <[email protected]>
* mesa: Trigger FBO validation on DrawBuffers change in non-ES2 mode.Eric Anholt2011-05-261-10/+26
| | | | | | | | | glDrawBuffers pointing at an unattached buffer is supposed to be incomplete without ARB_ES2_compatibility. The testcase to catch the bug of not implementing that bit of the spec was tricked by this missing piece of state update. Reviewed-by: Brian Paul <[email protected]>
* mesa: minor whitespace fixesBrian Paul2011-05-251-4/+4
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* mesa: plug in sync object display list functionsBrian Paul2011-05-251-0/+50
| | | | | Most just dispatch through to the immediate mode functions, except for glWaitSync(), per the extension spec.
* mesa: display list support for glProgramParameteriARB()Brian Paul2011-05-251-0/+30
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* mesa: plug shader object functions into display list dispatchBrian Paul2011-05-251-0/+2
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* mesa: plug in GL 3.0 ClearBuffer() display list functionsBrian Paul2011-05-251-5/+1
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* mesa: fill in missing sampler object display list functionsBrian Paul2011-05-251-0/+163
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* st/mesa: simplify some st_context(ctx)->pipe codeBrian Paul2011-05-256-10/+9
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* st/mesa: fix incorrect texture level/face/slice accessesBrian Paul2011-05-252-12/+21
| | | | | | | | | | If we use FBOs to access mipmap levels with glRead/Draw/CopyPixels() we need to be sure to access the correct mipmap level/face/slice. Before, we were just passing zero in quite a few places. This fixes the new piglit fbo-mipmap-copypix test. NOTE: This is a candidate for the 7.10 branch.
* i915g: Bump texture sizesJakob Bornecrantz2011-05-251-2/+2
| | | | | | Spotted and tested by Christopher Egert. Signed-off-by: Jakob Bornecrantz <[email protected]>
* i965: Warnings cleanup.Eric Anholt2011-05-252-4/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix assertion failures in unused brw_reg setup by deleting it.Eric Anholt2011-05-251-1/+0
| | | | | | | I was using undefined values to create an unused value. Go me. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37366 Reviewed-by: Kenneth Graunke <[email protected]>
* r600g: remove duplicate opcode in r600_opcodes.hAlex Deucher2011-05-251-1/+0
| | | | | | | | V_SQ_CF_WORD1_SQ_CF_INST_HALT is 0x1f on both evergreen and cayman. Reported-by: Gustaw Smolarczyk <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* intel: Change FBO validation criteria to accomodate hiz and seprate stencilChad Versace2011-05-251-15/+27
| | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Fix intel_draw_buffer() to accomodate hiz and separate stencilChad Versace2011-05-251-5/+11
| | | | | | | | The logic of intel_draw_buffers() expected that stencil buffers were always combined depth/stencil. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add hiz_region to intel_mipmap_treeChad Versace2011-05-253-0/+36
| | | | | | | | | | When a texture is attached to multiple FBO's, a separate renderbuffer wrapper is created for each attachment. This necessitates storing the hiz region for these renderbuffers in the texture itself instead of the renderbuffer wrapper. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Refactor the wrapping of textures with renderbuffersChad Versace2011-05-251-7/+8
| | | | | | | | | | | | | Before this commit, the renderbuffer's region was updated in intel_renderbuffer_texture(). This commit moves the update into intel_update_wrapper(), which is a more logical location for updates. This is in preparation for the next commit, which allocates and updates the texture's hiz region in intel_update_wrapper(). Having the two region updates located in the same function makes good form. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add hiz_region to intel_renderbufferChad Versace2011-05-252-0/+46
| | | | | | | | | | | | | | | | | | | | | | A hiz surface must be supplied to the hardware when rendering to a depth buffer with hiz. There are three potential places to store that surface: 1. Allocate a larger intel_region for the depthbuffer, and let the region's tail be the hiz surface. 2. Allocate a separate intel_region for hiz, and store it as brw_context state. 3. Allocate a separate intel_region for hiz, and store it in intel_renderbuffer. We choose method 3. Method 1 has not been chosen due to future complications it might cause when requesting a DRI drawable's depth buffer attachment from X. Method 2 has not been chosen because storing the hiz region apart from the depth region makes lazy hiz/depth resolves difficult to implement. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add is_hiz_depth_format() to intel_contex.vtblChad Versace2011-05-253-0/+24
| | | | | | | | | Given a format, is_hiz_depth_format() indicates if HiZ can be enabled on a depthbuffer of that format. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Allocate region for separate stencil bufferChad Versace2011-05-251-3/+30
| | | | | | | | | ... in intel_alloc_renderbuffer_storage(). The stencil buffer has quirky pitch requirements, so its region allocation is a special case. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Change supported texture formats for separate stencilChad Versace2011-05-252-1/+7
| | | | | | | | | | | When hardware supports separate stencil, enable support for separate depth/stencil texture formats in the table intel_context.ctx.TextureFormatsSupported. If the hardware must use separate stencil, then disable support for combined depth/stencil formats. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* mesa: Add MESA_FORMAT_X8_Z24 to _mesa_choose_tex_formatChad Versace2011-05-251-0/+2
| | | | | | | | | | | Prefer MESA_FORMAT_X8_Z24 over MESA_FORMAT_S8_Z24 for textures with internal format GL_DEPTH_COMPONENT*. i965 needs MESA_FORMAT_X8_Z24 for HiZ and separate stencil. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add flags to intel_context for hiz and separate stencilChad Versace2011-05-252-0/+58
| | | | | | | | | | | | | | | | | | | Add the following flags: intel_context.has_separate_stencil intel_context.must_use_separate_stencil intel_context.has_hiz The flags are currently set to false, and will be enabled for a given chipset once the feature is completely implemented. Since it may be some time before these features are completed, their values can be overridden with environment variables INTEL_HIZ and INTEL_SEPARATE_STENCIL. Valid values for these environment variables are "0" and "1". Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
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