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* iris: Bail resource creation upon aux creation errorNanley Chery2019-10-291-16/+17
| | | | | | | | The functions used during aux buffer configuration and creation only return false for exceptional errors. Don't proceed with surface creation in those cases. Reviewed-by: Jordan Justen <[email protected]>
* iris: Drop iris_resource::aux::extra_aux::boNanley Chery2019-10-292-16/+3
| | | | | | | | The primary and secondary aux buffers are always allocated in the same BO. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* zink: pass line width from rast_state to gfx_pipeline_state.Duncan Hopkins2019-10-291-1/+3
| | | | Reviewed-by: Erik Faye-Lund <[email protected]>
* anv: Reduce the minimum number of relocationsJason Ekstrand2019-10-291-1/+1
| | | | | | | | | | The original value of 256 was under the assumption that you're a batch buffer which is likely going to have a large number of relocations. However, pipeline objects on Gen7 will have at most 6 relocations (one per shader stage and one for the workaround BO) so this is a lot of per-pipeline wasted space. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Delay allocation of relocation listsJason Ekstrand2019-10-291-67/+71
| | | | | | | | | | | | | The old relocation list code always allocated 256 relocations and a hash set up-front without knowing whether or not we really need them. In particular, in the softpin case, this is two fairly large allocations that we don't need to be making. Also, for pipeline objects on haswell where we don't have softpin, we don't need relocations unless scratch is used so this is extra data per-pipeline. Instead, we should do it on-demand. This shaves 3.5% off of a cpu-limited example running with the Dawn WebGPU implementation. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Implement new way for setting streamout buffers.Plamena Manolova2019-10-293-0/+19
| | | | | | | | | For gen12 we set the streamout buffers using 4 separate commands instead of 3DSTATE_SO_BUFFER. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Implement new way for setting streamout buffers.Plamena Manolova2019-10-292-3/+23
| | | | | | | | | For gen12 we set the streamout buffers using 4 separate commands instead of 3DSTATE_SO_BUFFER. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
| | | | | | | | For gen12 we set the streamout buffers using 4 separate commands instead of 3DSTATE_SO_BUFFER. Signed-off-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* freedreno/a6xx: add a618 supportRob Clark2019-10-293-0/+27
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: cleanup magic registersRob Clark2019-10-296-22/+47
| | | | | | | | Extract out values for the handful of unknown registers which have different values across different a6xx models, to simplify adding support for new a6xx's. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: remove some left over dead codeRob Clark2019-10-291-10/+0
| | | | | | These registers don't exist, just remnants of initial port from a5xx. Signed-off-by: Rob Clark <[email protected]>
* anv: Set depthBounds to true in anv_GetPhysicalDeviceFeatures.Plamena Manolova2019-10-291-1/+1
| | | | | | | | | Add depth bounds testing to the list of supported physical device features. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
| | | | | | | | | The bias for the 3DSTATE_DEPTH_BOUNDS instruction should be 2 not 1. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* gallium/swr: Enable GL_ARB_gpu_shader5: multiple streamsKrzysztof Raszkowski2019-10-296-14/+78
| | | | | | | Added support for geometry shader multiple streams (part of GL_ARB_gpu_shader5 extension). Reviewed-by: Jan Zielinski <[email protected]>
* panfrost: Remove unused definitions in mali-job.hAlyssa Rosenzweig2019-10-291-9/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Cleanup _shader_upper -> shaderAlyssa Rosenzweig2019-10-293-17/+14
| | | | | | I don't believe this is actually a tagged pointer; warn if it is. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* intel/perf: update ICL configurationsLionel Landwerlin2019-10-291-59/+28
| | | | | | | | | A few equations/programming changes for ICL. v2: Fix a couple of issues in naming and floating/integer operations (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* anv: Fix output of INTEL_DEBUG=bat for chained batchesCaio Marcelo de Oliveira Filho2019-10-281-1/+1
| | | | | | | | | | The anv_batch_bo contents are linked one to another, and when printing we have to start with the first of those. Since in `u_vector` new elements are added to the head, to get the first element we need the vector's tail. Fixes: 32ffd90002b ("anv: add support for INTEL_DEBUG=bat") Reviewed-by: Lionel Landwerlin <[email protected]>
* winsys/amdgpu: use the new GPU reset queryMarek Olšák2019-10-281-20/+37
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* ac: get tcc_harvested from the kernelMarek Olšák2019-10-281-3/+8
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: initialize shader compilers in threads on demandMarek Olšák2019-10-284-8/+14
| | | | | | It takes a noticable amount of time with piglit. Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: don't print diagnostic LLVM remarks and notesMarek Olšák2019-10-281-6/+3
| | | | | | We don't use them. Reviewed-by: Timothy Arceri <[email protected]>
* aco: Introduce vgpr_limit to keep track of available VGPRs.Timur Kristóf2019-10-286-5/+12
| | | | | Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Implement subgroup shuffle in GFX10 wave64 mode.Timur Kristóf2019-10-286-16/+113
| | | | | | | | | | | | | Previously subgroup shuffle was implemented using the bpermute instruction, which only works accross half-waves, so by itself it's not suitable for implementing subgroup shuffle when the shader is running in wave64 mode. This commit adds a trick using shared VGPRs that allows to implement subgroup shuffle still relatively effectively in this mode. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Remove dead code in reduction lowering.Rhys Perry2019-10-281-16/+14
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Fix reductions on GFX10.Rhys Perry2019-10-283-18/+95
| | | | | | | | Fixes p_reduce (all cluster sizes), p_inclusive_scan and p_exclusive_scan with all reduction operations. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* loader: default to iris for all future PCI IDsEric Engestrom2019-10-284-20/+5
| | | | | | | | | | The existing "fallback" code didn't actually do anything, so this removes it, and instead we just always fallback to `iris` for future PCI IDs. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: add a couple printflike() annotationsEric Engestrom2019-10-281-2/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* st/mesa: lower global vars to local after lowering clipErik Faye-Lund2019-10-281-0/+1
| | | | | | | | | | | | | | | | When this code was merged, this wasn't necessary because the state-tracker would do it later anyway. But this recently got changed, without changing the code that depended on this. Arguably, this was a mistake in the lowering pass to begin with. Either way, let's fix it by not assuming that the lowering code gets called later when it's not needed. This fixed user-defined clip-planes in Zink. Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: eaffdad1082 ("st/mesa: don't lower_global_vars_to_local for VS if there are no dead inputs") Reviewed-by: Marek Olšák <[email protected]>
* iris: Create resource with aux_usage MCS_CCSSagar Ghuge2019-10-281-1/+2
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Support lossless compression with multisamplesSagar Ghuge2019-10-281-5/+1
| | | | | | | | | | GEN12 adds the ability to losslessly compress each sample plane in a multisampled buffer that uses MCS compression. v2: Remove unnecessary assertion (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Get correct resource aux usage for copySagar Ghuge2019-10-281-0/+1
| | | | | | | | | | Add case for MCS_CCS so that we get the correct aux usage while copy operation. v2: Fix commit subject (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Use isl_aux_usage_has_mcs instead of comparingSagar Ghuge2019-10-281-5/+7
| | | | | | | | | | | | Depending on MCS_CSS or MCS we can emit blorp blit shaders. As we support MCS_CSS and MCS, it makes sense to use isl_aux_usage_has_mcs function. v2: Fix commit message (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Define MCS_CCS state transitions and usagesSagar Ghuge2019-10-282-5/+10
| | | | | | | | v2: 1) Fix assertion check (Nanley Chery) 2) Correct commit subject (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Initialize CCS to fast clear while using with MCSSagar Ghuge2019-10-281-3/+14
| | | | | | | | | | v2: Explain Bsepc quotes properly (Nanley Chery) v3: 1) Fix comment format (Nanley Chery) 2) Fix typo in comment (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Don't reconfigure aux surfaces for MCSSagar Ghuge2019-10-281-0/+3
| | | | | | | | | If aux for MCS is already configured, don't configure again. v2: Fix missing period in commit message (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* zink: emulate optional depth-formatsErik Faye-Lund2019-10-286-8/+42
| | | | | | | | | | | | | | | The Vulkan spec says that an implementation has to support one of VK_FORMAT_X8_D24_UNORM_PACK32 and VK_FORMAT_D32_SFLOAT, as well of one of VK_FORMAT_D24_UNORM_S8_UINT and VK_FORMAT_D32_SFLOAT_S8_UINT. So let's keep track which one is supported of earch pair, and emulate one on top of the other one. This won't give the exact result for comparisons, or when mapping and unmapping the resources. But it's better than flat out failing to create the resource, and we can fix the map/unmap issue later if needed. Tested-by: Duncan Hopkins <[email protected]>
* zink: error if VK_KHR_maintenance1 isn't supportedErik Faye-Lund2019-10-282-2/+7
| | | | | While we're at it, remove the VK_-prefix from the extension bool; all extensions have this so it's kinda superfluous.
* iris: Disallow incomplete resource creationNanley Chery2019-10-281-2/+6
| | | | | | | | If a modifier specifies an aux, it must be created. Fixes: 75a3947af46 ("iris/resource: Fall back to no aux if creation fails") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Don't leak the resource for unsupported modifierNanley Chery2019-10-281-1/+1
| | | | | | | | Make sure the res struct is free'd before returning. Fixes: 2dce0e94a3d ("iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Enable HIZ_CCS samplingNanley Chery2019-10-283-8/+24
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Satisfy clear color rules for HIZ_CCSNanley Chery2019-10-281-1/+35
| | | | | | | | | Store the converted depth value into two dwords. Avoids regressing the piglit test "fbo-depth-array depth-clear", when HIZ_CCS sampling is enabled in a later commit. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Fix and use HIZ_CCS write through modeNanley Chery2019-10-282-0/+7
| | | | | | | | Write through to the CCS if the surface is used as a texture and can be sampled by the HW with CCS. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Start using blorp_can_hiz_clear_depth()Nanley Chery2019-10-281-1/+7
| | | | | | | | Check that the alignment requirements for HIZ_CCS are satisfied by using this function. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Satisfy HIZ_CCS fast-clear alignmentsNanley Chery2019-10-281-0/+47
| | | | | | | | Prevent the piglit test, amd_vertex_shader_layer-layered-depth-texture-render, from regressing in in a future commit. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Refactor blorp_can_hiz_clear_depth()Nanley Chery2019-10-283-16/+19
| | | | | | | Prepare this function to be used in iris and to handle new Gen12 behavior. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* isl: Add isl_surf_supports_hiz_ccs_wt()Nanley Chery2019-10-282-0/+18
| | | | | | | | Add a helper to determine if an ISL surface supports the write-through mode of HIZ_CCS. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Enable HIZ_CCS in depth buffer instructionsNanley Chery2019-10-282-3/+7
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Define initial HIZ_CCS state and transitionsNanley Chery2019-10-283-13/+20
| | | | | | | Make it match those of HIZ. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Create an unusable secondary aux surfaceNanley Chery2019-10-282-6/+49
| | | | | | | | | | | | The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers store information about two aux buffers. We choose to represent this as HiZ/MCS being the primary aux surface and the CCS as an secondary/extra aux surface. This representation has the effect of placing most of the code that will have to choose between the two aux surfaces around the aux-map entry points. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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