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* gallivm/ppc64le: adjust VSX code generation control.Ben Crocker2017-10-051-7/+30
| | | | | | | | | | | | | | | | | | | | | | | In lp_build_create_jit_compiler_for_module(), advance the minimum version of LLVM for VSX code generation to 4.0; this is the minimum revision at which several known VSX code generation bugs are fixed: https://llvm.org/bugs/show_bug.cgi?id=25503 (fixed in 3.8.1) https://llvm.org/bugs/show_bug.cgi?id=26775 (fixed in 3.8.1) https://llvm.org/bugs/show_bug.cgi?id=33531 (fixed in 4.0) An llc performance bug introduced in LLVM 4.0, https://llvm.org/bugs/show_bug.cgi?id=34647 is still pending as of LLVM 5.0, but only has a pronounced effect on one of the Piglit tests: ext_transform_feedback-max-varyings. All changes tested via Piglit. Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* gallivm: allow additional llc optionsBen Crocker2017-10-051-0/+23
| | | | | | | | | | | | | | | | In init_native_targets, allow the passing of additional options to the LLC compiler via new GALLIVM_LLC_OPTIONS environmental control. This option is available only #ifdef DEBUG, initially. At top, add #include <llvm-c/Support.h> for LLVMParseCommandLineOptions() declaration. v2: Fix compile error with old llvm versions (sroland) Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix typo in debug_printf messageBen Crocker2017-10-051-1/+1
| | | | | | | | | | In gallivm_compile_module, fix a typo in the debug_printf("Invoke as \"llc ..." message. Cc: "17.2" <[email protected]> Signed-off-by: Ben Crocker <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radv: remove useless checks around radv_CmdBindPipeline()Samuel Pitoiset2017-10-048-97/+34
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: check that pipeline is different before binding itSamuel Pitoiset2017-10-041-2/+8
| | | | | | | | We only need to dirty the descriptors when the pipeline is a new one, because user SGPRs can be potentially different. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Validate "Special Requirements for Handling Double Precision Data Types"Matt Turner2017-10-042-0/+792
| | | | | | | | | | | | | I did not implement: CNL's restriction on 64-bit int + align16, because I don't think we'll ever use this combination regardless of hardware generation. The restriction on immediate DF -> F conversions, because there's no reason to ever generate that, and I don't even know how DF -> F conversions are supposed to work in Align16 since (1) the dst stride must be 1, but (2) the dst stride would have to be 2 for src and dst strides to be aligned.
* i965: Fix and enable forgotten validation testMatt Turner2017-10-041-14/+17
| | | | I seem to have forgotten I still had work to do.
* i965: Only insert error message if not already presentMatt Turner2017-10-041-5/+13
| | | | | | | Some restrictions require something like strides to match between src and dest. For multi-source instructions, I'd rather encapsulate the logic for not inserting already present errors in ERROR_IF than open-coding it multiple places.
* i965: Avoid validation error when src1 is not presentMatt Turner2017-10-041-1/+1
| | | | | There can be no violation of the restriction that source offsets are aligned if there is only one source offset.
* i965: Remove validate_reg()Matt Turner2017-10-041-80/+0
| | | | | Replaced by the assembly validator, and in fact gets in the way of writing tests for the assembly validator.
* i965: Add and use STRIDE and WIDTH macrosMatt Turner2017-10-041-18/+15
| | | | | | You'll notice there were bugs in some of the code being replaced. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add parentheses around usage of macro argumentsMatt Turner2017-10-041-1/+1
| | | | | | Otherwise I cannot use this macro in test_eu_validate.cpp Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add GLK, CFL, CNL to test_eu_validate.cMatt Turner2017-10-041-0/+7
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* i965: Add Atom graphics names to parse_devid_override()Matt Turner2017-10-041-0/+3
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* i965: Fix support for disassembling 64-bit integer immediatesMatt Turner2017-10-041-2/+2
| | | | | | | The type suffixes were wrong, and the 16 was missing the 0 prefix. Fixes: 92f787ff86ab ("i965: Add support for disassembling 64-bit integer immediates") Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Rewrite fsign64 to skip the float -> double conversionMatt Turner2017-10-041-41/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | ... without the float -> double conversion. Low power parts have additional restrictions when it comes to operating on 64-bit types, and the instruction used to do the conversion violates one of them: specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword". Previously we generated a float and then converted, but we can avoid the conversion by using the same extract-the-sign-bit + or-in-1.0 algorithm by directly operating on the high four bytes of each double-precision component in the result. In SIMD8 and SIMD16 this cuts one instruction from the implementation, and more importantly that instruction is the one which violated the regioning restriction. Along the way I removed some comments that I did not think helped, and some code about double comparisons which does not seem to be necessary today. This prevents validation failures caught by the new EU validation code added in later patches. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Unpack count argument to 64-bit shift ops on AtomMatt Turner2017-10-041-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | 64-bit operations on Atom parts have additional restrictions over their big-core counterparts (validated by later patches). Specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword" is violated by most shift operations since NIR uses a 32-bit value as the shift count argument, and this causes instructions like shl(8) g19<1>Q g5<4,4,1>Q g23<4,4,1>UD where src1 has a 32-bit stride, but the dest and src0 have a 64-bit stride. This caused ~4 pixels in the ARB_shader_ballot piglit test fs-readInvocation-uint.shader_test to be incorrect. Unfortunately no ARB_gpu_shader_int64 test hit this case because they operate on uniforms, and their scalar regions are an exception to the restriction. We work around this by effectively unpacking the shift count, so that we can read it with a 64-bit stride in the shift instruction. Unfortunately the unpack (a MOV with a dst stride of 2) is a partial write, and cannot be copy-propagated or CSE'd. Bugzilla: https://bugs.freedesktop.org/101984
* i965/fs: Don't apply POW/FDIV workaround on Gen10+Matt Turner2017-10-041-0/+1
| | | | | | The documentation says it applies only to Gens 8 and 9. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Fix src0 vs src1 typoMatt Turner2017-10-041-1/+1
| | | | | | | | | | | | | | | | A typo caused us to copy src0's reg file to src1 rather than reading src1's as intended. This caused us to fail to compact instructions like mov(8) g4<1>D 0D { align1 1Q }; because src1 was set to immediate rather than architecture file. Fixing this reenables compaction (after the precompact() pass changes the data types): mov(8) g4<1>UD 0x00000000UD { align1 1Q compacted }; Fixes: 1cb0a7941b27 ("i965: Switch to using the logical register types") Reviewed-by: Kenneth Graunke <[email protected]>
* radv: enable tc compatible htile for d32s8 also.Dave Airlie2017-10-041-1/+2
| | | | | | | | | | | | This enables tc compatible htile for stencil surfaces as well. This gives a 3-5fps boost on Mad Max on high@4k. It also depends on Bas's tc-compat htile patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: dump SPIRV when a GPU hang is detectedSamuel Pitoiset2017-10-044-4/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: dump NIR when a GPU hang is detectedSamuel Pitoiset2017-10-044-11/+27
| | | | | | | | This looks a bit ugly to me, but the existing codepath is not terribly elegant as well. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: silence a warningMarek Olšák2017-10-041-1/+3
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* egl/wayland: Don't use dmabuf with no modifiersDaniel Stone2017-10-041-7/+11
| | | | | | | | | | | | | | | | | The dmabuf interface requires a valid modifier to be sent. If we don't explicitly get a modifier from the driver, we can't know what to send; it must be inferred from legacy side-channels (or assumed to linear, if none exists). If we have no modifier, then we can only have a single-plane format anyway, so fall back to the old wl_drm buffer import path. Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them") Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers") Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reported-by: Andy Furniss <[email protected]> Cc: Marek Olšák <[email protected]>
* egl/wayland: Check queryImage return for wl_bufferDaniel Stone2017-10-041-15/+41
| | | | | | | | | | | | | | | When creating a wl_buffer from a DRIImage, we extract all the DRIImage information via queryImage. Check whether or not it actually succeeds, either bailing out if the query was critical, or providing sensible fallbacks for information which was not available in older DRIImage versions. Fixes: a65db0ad1c ("st/dri: don't expose modifiers in EGL if the driver doesn't implement them") Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers") Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reported-by: Andy Furniss <[email protected]> Cc: Marek Olšák <[email protected]>
* wayland-egl: adds CFLAGS for wayland.egl.h includeTobias Klausmann2017-10-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with commit ab0589c6ed ("wayland-egl: remove no longer needed wayland-client dependency") the wayland-egl.h include was missing leading to a build failure: CC wayland-egl.lo wayland-egl.c:33:10: fatal error: wayland-egl.h: No such file or directory #include "wayland-egl.h" ^~~~~~~~~~~~~~~ Strictly speaking we should be checking for wayland-egl in configure and propagating its CFLAGS here. Yet again, the current wayland-egl split is bonkers as the Wayland repo provides single header, no pkg-config file or library. That will be resolved at a later stage, but in the meanwhile fix the build. Fixes: ab0589c6ed ("wayland-egl: remove no longer needed wayland-client dependency") Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Emil Velikov <[email protected]> [Emil Velikov: add some text about CFLAGS and current wayland-egl situation] Signed-off-by: Emil Velikov <[email protected]>
* automake: add texcompress_s3tc_tmp.h to the sources listEmil Velikov2017-10-041-0/+1
| | | | | | | | Otherwise it will be missing from the tarball. Fixes: f7daa737d17 ("mesa: Combine libtxc_dxtn sources into texcompress_s3tc_tmp.h") Signed-off-by: Emil Velikov <[email protected]>
* st/va: add RGB support to vlVaPutSurfaceLeo Liu2017-10-041-1/+13
| | | | | Tested-by: Andy Furniss <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: don't re-allocate interlaced buffer with pakced formatLeo Liu2017-10-041-4/+6
| | | | | | | | | | | It caused corruption, when vlVaPutImage putting raw data to the fields v2: add RGB formats since it got uploaded here as well Cc: [email protected] Cc: Andy Furniss <[email protected]> Tested-by: Andy Furniss <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/vdpau: don't re-allocate interlaced buffer with packed YUV formatLeo Liu2017-10-041-0/+2
| | | | | | | | | It caused corruption, when vlVdpVideoSurfacePutBitsYCbCr putting YUV to the fields Cc: [email protected] Cc: Andy Furniss <[email protected]> Tested-by: Andy Furniss <[email protected]> Reviewed-by: Christian König <[email protected]>
* radv: Implement TC compatible HTILE.Bas Nieuwenhuizen2017-10-044-6/+62
| | | | | | | The situations where we enable it are quite limitied, but it works, even for madmax, so lets just enable it. Reviewed-by: Dave Airlie <[email protected]>
* radv: emit fmuladd instead of fma to llvm.Dave Airlie2017-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | For Vulkan SPIR-V the spec states fma() Inherited from OpFMul followed by OpFAdd. Matt says the backend will do the right thing depending on the hardware being compiled for, if you use the fmuladd intrinsic. Using the Mad Max pts test, on high settings at 4K: CHP: 55->60 HGDD: 46->50 LM: 55->60 No change on Stronghold. Thanks to Feral for spending the time to track this down. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* android: fix build issues with brw_nir_trig_workarounds.cTapani Pälli2017-10-041-1/+1
| | | | | | Fixes: 848da66222 ("intel: use a flag instead of setting PYTHONPATH") Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel: compiler: vec4: add missing default 0 lodLionel Landwerlin2017-10-031-0/+9
| | | | | | | | | We set a similar default value for LOD in the fs backend for TXS/TXL. Without this we end up generating invalid MOV with a null src. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: "17.2 17.1" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* anv: Remove base_vertex/instance from push_constantsJason Ekstrand2017-10-031-7/+0
| | | | | | | This is just legacy cruft. We don't push these values; we pass them in as vertex attributes. Reviewed-by: Lionel Landwerlin <[email protected]>
* util: include string.h in u_string.hBrian Paul2017-10-031-0/+1
| | | | | | | To fix MinGW compiler warning about missing strlen() prototype. Not sure how I missed this when fixing the malloc() / stdlib.h issue. Reviewed-by: Charmaine Lee <[email protected]>
* llvmpipe: silence 'variable may be used uninitialized' warningsBrian Paul2017-10-032-2/+2
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* mesa: silence 'variable may be used uninitialized' warning in teximage.cBrian Paul2017-10-031-1/+1
| | | | | | Found with MinGW optimized build. Reviewed-by: Charmaine Lee <[email protected]>
* mesa: silence 'variable may be used uninitialized' warning in bufferobj.cBrian Paul2017-10-031-0/+1
| | | | | | Found with MinGW optimized build. Reviewed-by: Charmaine Lee <[email protected]>
* svga: wrap long comments in svga_tgsi_vgpu10.cBrian Paul2017-10-031-4/+6
| | | | Trivial.
* svga: tweak pre-VGPU10 rasterization offsetsBrian Paul2017-10-031-17/+7
| | | | | | | | | | | | | | | | | | | | It seems there's no perfect x/y biases for line drawing to satisfy all applications. Depending on the biases, either real apps produce results similar to VGPU10 while Piglit's gl-1.0-ortho-pos fails, or vice versa. Let's lean toward real applications (Solidworks, SolidEdge, Google Earth) over Piglit. Using (-0.5, -0.5) for points, lines and triangles, seems to generally work well. We don't seem to have these issues with VGPU10. Tested with Piglit and CAD-oriented apitraces. See VMware bugs 1775498 and 1905053. Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: if we get nr_samples==1, store nr_samples=0Brian Paul2017-10-031-4/+7
| | | | | | | | | | We need to be more careful not to treat nr_samples=1 as an msaa surface. This patch prevents us from errantly declaring an MSAA shader resource with 1 sample. No Piglit regressions, fixes the above-described errors. Reviewed-by: Neha Bhende <[email protected]>
* svga: emit sampler constants only if sampler view existsCharmaine Lee2017-10-031-7/+12
| | | | | | | | | | | | | | It is possible to have holes in the shader emitter's sampler_target array. 0 sampler_target does not necessarily mean there is no sampler view specified since texture buffer target has the value 0. With this patch, a sampler_view array is added to the shader emitter structure to specify if there is a sampler view for each texture unit. Only if there is a sampler view, we will emit constant for texcoord scale factor or texture buffer size for that sampler view. Fixes a rendering issue with Turbine after commit 1020e960440. Reviewed-by: Brian Paul <[email protected]>
* svga: fix incorrect case in svga_typeless_format()Brian Paul2017-10-031-2/+1
| | | | | | | | | | | | For the case of SVGA3D_X32_G8X24_UINT we incorrectly returned SVGA3D_R32_FLOAT_X8X24. We should return SVGA3D_R32G8X24_TYPELESS. Note that we never actually use SVGA3D_X32_G8X24_UINT so this has no impact. No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* svga: add typeless switch cases in svga_typeless_format()Brian Paul2017-10-031-0/+10
| | | | | | | | | | We sometimes pass typeless formats to this function. By adding switch cases we avoid the "Unexpected format XXX in svga_typeless_format" warning messages. No functional change. No Piglit regressions, no above-mentioned warning messages. Reviewed-by: Charmaine Lee <[email protected]>
* svga: Allow sRGB format with PIPE_BIND_DISPLAY_TARGET binding flag on vgpu10.Neha Bhende2017-10-031-2/+7
| | | | | | | This patch allows to use sRGB formats for DISPLAY_TARGET on vgpu10. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* etnaviv: Set up unknown GC3000 statesWladimir J. van der Laan2017-10-031-0/+11
| | | | | | | | | | | Set up new states that the blob started setting for GC3000 consistently. This makes sure that when another test or driver leaves the GPU in unpredictable state, these states are set up correctly for our rendering. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Fix point sprite rendering on GC3000Wladimir J. van der Laan2017-10-031-0/+2
| | | | | | | | Setting PA_VIEWPORT_UNK state correctly is necessary to make point sprite rendering on GC3000 work. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Add support for DP2 instructionWladimir J. van der Laan2017-10-034-1/+7
| | | | | | | | A two-component dot product instruction is supported with HALTI2, use it on hardware that supports it. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Support opcodes with bit 6 set in assemblerWladimir J. van der Laan2017-10-031-1/+4
| | | | | | | | Support opcodes with bit 6 set in assembler, and assert that only ops 0x00..0x7f are used. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
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