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* i965/wm: use binding size for ubo/ssbo when automatic size is unsetIlia Mirkin2016-01-051-4/+10
* Revert "i965/wm: use proper API buffer size for the surfaces."Ilia Mirkin2016-01-054-13/+5
* st/mesa: make KHR_debug output independent of context creation flags (v2)Nicolai Hähnle2016-01-044-57/+98
* nvc0: scale up inter_bo size so that it's 16M for a 4K videoIlia Mirkin2016-01-041-2/+5
* nv50,nvc0: fix crash when increasing bsp bo size for h264Ilia Mirkin2016-01-042-4/+4
* i965/wm: use proper API buffer size for the surfaces.Samuel Iglesias Gonsálvez2016-01-044-5/+13
* radeonsi: remove unused parameter from si_shader_binary_read_configMarek Olšák2016-01-033-10/+7
* radeonsi: move si_shader_binary_upload out of si_shader_binary_readMarek Olšák2016-01-033-11/+10
* gallium/radeon: dump LLVM module outside of radeon_llvm_compileMarek Olšák2016-01-034-9/+12
* gallium/radeon: always add +DumpCode to the LLVM target machine for LLVM <= 3.5Marek Olšák2016-01-034-6/+5
* gallium/radeon: r600_can_dump_shader should get TGSI processor type directlyMarek Olšák2016-01-034-15/+10
* radeonsi: pass TGSI processor type to si_shader_binary_read for dumpingMarek Olšák2016-01-033-4/+5
* radeonsi: pass TGSI processor type to si_compile_llvm for dumpingMarek Olšák2016-01-033-5/+5
* radeonsi: rename shader parameter definitions and variables for more clarityMarek Olšák2016-01-033-43/+43
* nvc0/ir: add support for PK2H/UP2HIlia Mirkin2016-01-034-2/+28
* st/mesa: use PK2H/UP2H when supportedIlia Mirkin2016-01-033-5/+14
* gallium: add PIPE_CAP_TGSI_PACK_HALF_FLOAT to indicate UP2H/PK2H supportIlia Mirkin2016-01-0316-0/+17
* tgsi: update PK2H/UP2H channel behavior infoIlia Mirkin2016-01-031-8/+8
* gallium: document PK2H/UP2HIlia Mirkin2016-01-031-2/+14
* st/mesa: fix parameter names for tesseval/tessctrl prototypesSamuel Pitoiset2016-01-031-4/+4
* nouveau: fix double-const qualifierIlia Mirkin2016-01-032-2/+2
* freedreno/ir3: use NIR_PASS helper macrosRob Clark2016-01-031-19/+28
* nir: extract out helper macros for running passesRob Clark2016-01-032-36/+43
* freedreno/ir3: we require block_index metadataRob Clark2016-01-031-0/+2
* freedreno/ir3: refactor NIR IR handlingRob Clark2016-01-037-111/+202
* freedreno/ir3: drop unnecessary unreachable() caseRob Clark2016-01-031-2/+0
* gallium/tests: fix build with clang compilerSamuel Pitoiset2016-01-031-273/+330
* nv50,nvc0: optimize coherent buffer checking at draw timeSamuel Pitoiset2016-01-036-68/+82
* i965: Make TCS precompile use the TES primitive mode when available.Kenneth Graunke2016-01-021-1/+3
* i965: Push most TES inputs in SIMD8 mode.Kenneth Graunke2016-01-021-12/+30
* i965: Use LOAD_PAYLOAD for SIMD8 TES input loads, not MOV.Kenneth Graunke2016-01-021-1/+4
* i965: Move 3-src subnr swizzle handling into the vec4 backend.Kenneth Graunke2016-01-022-6/+18
* vc4: Fix build from upload changes.Eric Anholt2016-01-021-1/+1
* gallium/radeon: send LLVM diagnostics as debug messagesNicolai Hähnle2016-01-021-15/+46
* gallium/radeon: pass pipe_debug_callback into radeon_llvm_compile (v2)Nicolai Hähnle2016-01-027-9/+18
* radeonsi: send shader info as debug messages in addition to stderr outputNicolai Hähnle2016-01-021-14/+55
* radeonsi: pass pipe_debug_callback down into si_shader_binary_read (v2)Nicolai Hähnle2016-01-024-14/+22
* gallium/radeon: implement set_debug_callbackNicolai Hähnle2016-01-022-0/+14
* u_upload_mgr: allow specifying PIPE_USAGE_* for the upload bufferMarek Olšák2016-01-0217-26/+43
* u_upload_mgr: remove alignment parameter from u_upload_createMarek Olšák2016-01-0217-31/+19
* u_upload_mgr: pass alignment to u_upload_buffer manuallyMarek Olšák2016-01-023-2/+4
* u_upload_mgr: pass alignment to u_upload_data manuallyMarek Olšák2016-01-0219-22/+34
* u_upload_mgr: pass alignment to u_upload_alloc manuallyMarek Olšák2016-01-0225-27/+36
* u_upload_mgr: rework the application of alignmentMarek Olšák2016-01-021-10/+14
* st/mesa: fix GLSL uniform updates for glBitmap & glDrawPixels (v2)Marek Olšák2016-01-025-19/+25
* program: add _mesa_reserve_parameter_storageMarek Olšák2016-01-022-15/+36
* mesa: Fix warning with MESA_VERBOSE=api for BindBufferRangeJordan Justen2016-01-011-1/+1
* nv50,nvc0: make sure there's pushbuf space and that we ref the bo earlyIlia Mirkin2016-01-014-6/+5
* st/mesa: sort extensions enablement arrayIlia Mirkin2016-01-011-11/+11
* nir/lower_clip: add missing writemask on storeRob Clark2016-01-011-0/+1
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