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* i965/gen8 renderbuffer: Set depth size based on LOD0 for 3D texturesJordan Justen2014-05-131-1/+1
| | | | | | | | Fixes piglit's 'gl-3.2-layered-rendering-clear-color-all-types 3d mipmapped' Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/gen7 renderbuffer: Set depth size based on LOD0 for 3D texturesJordan Justen2014-05-131-1/+1
| | | | | | | | | | | | If blorp is disabled for color clears, then piglit's 'gl-3.2-layered-rendering-clear-color-all-types 3d mipmapped' will fail. Currently, gen8 fails similarly on this test because gen8 does not use blorp. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* freedreno/a3xx: add point-sizeRob Clark2014-05-131-4/+14
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-05-134-54/+252
| | | | Signed-off-by: Rob Clark <[email protected]>
* glsl_to_tgsi: remove unnecessary dead code elimination passBryan Cain2014-05-131-45/+5
| | | | | | | | | With the more advanced dead code elimination pass already being run, eliminate_dead_code was making no difference in instruction count, and had an undesirable O(n^2) runtime. So remove it and rename eliminate_dead_code_advanced to eliminate_dead_code. Reviewed-by: Marek Olšák <marek.olsak at amd.com>
* ralloc: Omit detailed license information about talloc.José Fonseca2014-05-131-4/+3
| | | | | | | | | | | | That information misleads source code auditing tools to think that ralloc itself is released under LGPL v3. Instead, simply state talloc is not licensed under a permissive license. v2: Use wording suggested by Kenneth. Reviewed-by: Brian Paul <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Avoid redundant call to brw_merge_inputs() in brw_try_draw_prims()Iago Toral Quiroga2014-05-131-7/+6
| | | | | | | | We always call brw_merge_inputs() right before looping over the primitives but this can be called inside the loop for each primitive too. In the case we do it for the first primitive the call is redundant and can be skipped. Reviewed-by: Eric Anholt <[email protected]>
* glsl: Do not call lhs->variable_referenced() multiple timesIago Toral Quiroga2014-05-131-3/+2
| | | | | | Instead take the result from the first call and use it where needed. Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Refactor state save/restore for framebuffer texture blitsTopi Pohjolainen2014-05-132-22/+52
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* wayland: Move version 2 request to end of interface specificationKristian Høgsberg2014-05-121-16/+19
| | | | | | | | | | We're moving towards requiring interface additions to be appended to the end of the interface block. No functional change, opcodes are assigned as before, but version 2 additions are now grouped together, which prevents a scanner warning. Cc: "10.2" <[email protected]> Signed-off-by: Kristian Høgsberg <[email protected]>
* glsl: the number of samplers is already calculated so use itTimothy Arceri2014-05-131-2/+1
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Stop doing remapping of "special" regs.Eric Anholt2014-05-121-37/+0
| | | | | | | | Now that we aren't using pixel_[xy] in live variables, nothing is looking at these regs after the visitor stage. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize the pixel_x/y workaround for all UW types.Eric Anholt2014-05-121-4/+4
| | | | | | | | | | | | | | | This is the only case where a fs_reg in brw_fs_visitor is used during optimization/code generation, and it meant that optimizations had to be careful to not move pixel_x/y's register number without updating it. Additionally, it turns out we had a couple of other UW values that weren't getting this treatment (like gl_SampleID), so this more general fix is probably a good idea (though I wasn't able to replicate problems with either pixel_[xy]'s values or gl_SampleID, even when telling the register allocator to reuse registers immediately) Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move has_hiz from the slice to the level.Eric Anholt2014-05-125-30/+25
| | | | | | | | The value depends only on the level, so no need to store the bool per slice. Shrinks intel_mipmap_slice from 24 bytes to 16, while slotting into an existing hole in intel_mipmap_level. Reviewed-by: Chad Versace <[email protected]>
* meta: Refactor configuration of renderbuffer samplingTopi Pohjolainen2014-05-122-13/+30
| | | | | | Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Refactor binding of renderbuffer as texture imageTopi Pohjolainen2014-05-122-30/+47
| | | | | | Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Merge compiling and linking of blit programTopi Pohjolainen2014-05-123-31/+39
| | | | | | Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Expose coordinate scissoring and mirroringTopi Pohjolainen2014-05-124-118/+213
| | | | | | Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Use helper variables for surface parametersTopi Pohjolainen2014-05-121-4/+8
| | | | | | Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nv50,nvc0: fix blit 3d path for 1d array texturesIlia Mirkin2014-05-111-0/+6
| | | | | | | | | | Need to adjust coordinates since the shader receives the array index as depth in z, but the TEX instruction expects it to be the second coordinate for a 1D array texture. This fixes fbo-generatemipmap-array. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.2" <[email protected]>
* nv50,nvc0: leave queries on during blit, turn them on for 2d engineIlia Mirkin2014-05-116-6/+35
| | | | | | | | Fixes the new logic of the conditional rendering piglit test. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.2" <[email protected]>
* mesa/st: leave current query enabled during glBlitFramebufferIlia Mirkin2014-05-113-0/+4
| | | | | | | | | Also make sure that pipe_blit_info gets zero'd out so that query isn't accidentally left enabled. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add bit to pipe_blit_info to leave current query enabledIlia Mirkin2014-05-111-0/+3
| | | | | | | | | | Previously the implication was that queries should be disabled during blits. However glBlitFramebuffer() is supposed to obey the current query, and this new bit will indicate that to the driver. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50: fix setting of texture ms info to be per-stageIlia Mirkin2014-05-113-6/+10
| | | | | | | | | | Different textures may be bound to each slot for each stage. So we need to be able to upload ms parameters for each one without stages overwriting each other. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.1 10.2" <[email protected]>
* nv50/ir: make sure to reverse cond codes on all the OP_SET variantsIlia Mirkin2014-05-111-1/+2
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Cc: "10.2 10.1" <[email protected]>
* freedreno/a2xx: fix compiler warningRob Clark2014-05-111-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: prepare depth export registers at compile timeMarek Olšák2014-05-103-14/+14
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: simplify depth/stencil export codeMarek Olšák2014-05-101-11/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: add support for non-scalar system valuesMarek Olšák2014-05-101-0/+6
| | | | | | The sample position is one of them. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add and use a helper function for loading constantsMarek Olšák2014-05-101-19/+19
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only count CS space for state atoms if we're going to drawMarek Olšák2014-05-101-5/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove unused variable exports_ps in si_pipe_shader_psMarek Olšák2014-05-101-12/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: use DRAW_PREAMBLE on CIKMarek Olšák2014-05-102-5/+10
| | | | | | | It's the same as setting the 3 regs separately, but shorter, and it also seems to be required on GFX7.2 and later. This doesn't fix Hawaii. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: simplify framebuffer state size computationMarek Olšák2014-05-101-26/+4
| | | | | | Take the upper bound. The number doesn't have to absolutely correct, only safe. Reviewed-by: Michel Dänzer <[email protected]>
* Revert "i965: Fix depth (array slices) computation for 1D_ARRAY render targets."Kenneth Graunke2014-05-092-5/+0
| | | | | | | | | | This reverts commit e6967270c75a5b669152127bb7a746d55f4407a6. Chris Forbes pointed out that this is broken for texture views which restrict the number of slices. He committed a better fix which makes this unnecessary. Cc: "10.2" <[email protected]>
* egl_dri2: cleanup memory leak in dri2_create_context()Emil Velikov2014-05-101-2/+3
| | | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* ilo: destroy the mutex, if winsys creation failsEmil Velikov2014-05-101-0/+1
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* glx/tests: Partially revert commit 51e3569573a7b3f8da0df093836761003fcdc414Emil Velikov2014-05-101-3/+3
| | | | | | | | | | | C++ does not support designated initializers, thus compilation is not guaranteed to succeed. Surprisingly gcc 4.6.3 fails to build the code, while version 4.9.0 compiles it without a hitch. Cc: "10.2" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78403 Signed-off-by: Emil Velikov <[email protected]> Tested-by: Vinson Lee <[email protected]>
* mesa: propagate FragDepthLayout to gl_programChia-I Wu2014-05-091-0/+5
| | | | | | | | The information was lost during linking, causing the layout to be treated as FRAG_DEPTH_LAYOUT_NONE. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Rename linker's is_varying_varChris Forbes2014-05-101-3/+3
| | | | | | | | | | | | | Both the ast->IR and linker have functions with this name, but different behavior. Rename the linker's version to var_counts_against_varying_limit to be closer to what it is actually used for. Suggested by Ian a while back. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix GPU hangs on Broadwell in shaders with some control flow.Kenneth Graunke2014-05-091-7/+7
| | | | | | | | | | | | | | | | | | According to the documentation, we need to set the source 0 register type to IMM for flow control instructions that have both JIP and UIP. Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests, Unigine Crypt, a WebGL raytracer demo, and several Steam titles. Cc: "10.2" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939 Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Topi Pohjolainen <[email protected]> Tested-by: Kristian Høgsberg <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radeonsi: Enable geometry shaders with LLVM 3.4.1Tom Stellard2014-05-094-9/+13
| | | | | | Reviewed-by: Michel Dänzer <[email protected]> CC: "10.1 10.2" <[email protected]>
* st/xa: Fix performance regression introduced by commit "Cache render target ↵Thomas Hellstrom2014-05-091-1/+1
| | | | | | | | | | | | surface" The mentioned commit has the nasty side-effect of turning off accelerated copies. Cc: "10.1 10.2" <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* clover: Destory pipe_screen when device does not support compute v2Tom Stellard2014-05-091-1/+4
| | | | | | | | v2: - Make sure screen was successfully created before destroying it. Cc: "10.2" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* pipe-loader: Don't destroy the winsys in the sw loaderTom Stellard2014-05-091-3/+0
| | | | | | | | | | | | | The screen takes ownership of the winsys, and is responsible for destroying it. Users of pipe-loader should make sure they destory and screens they've created to avoid memory leaks. This fixes a crash in clover introduced by ce6c17c0833032e91a2d1b34f9eb80c738a854a2 where the pipe-loader was destroying the winsys while a screen was still using it. Cc: "10.2" <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/Gen8: Set up layer constraints properly for depth buffersChris Forbes2014-05-091-9/+6
| | | | | | | | | | | | | | | | | Same issues as the previous commit fixed for Gen7: - Bogus physical->logical layer conversion; depth/stencil surfaces are still IMS layout on Gen8. - mt_layer ignored in layered rendering case, which breaks handling of views with MinLayer. - Render target array extent not set correctly for arrays. I'm not able to test this one since I can't get a Broadwell yet, but it's the same set of fixes as for Gen7. V2: Restore the MAX2() to account for zero depth/layer_count. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen7: Set up layer constraints properly for depth buffersChris Forbes2014-05-091-9/+6
| | | | | | | | | | | | | | | Again, a few problems: - Layered attachments did not honor MinLayer. - Non-layered MSAA attachments rendered to the wrong layer due to dividing by the layer count. All depth buffers use the IMS layout, so the physical layer count == logical layer count. - Layered attachments were not limited to irb->layer_count, so we could render off the end of the texture. V2: Restore the MAX2() to account for zero depth/layer_count. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen8: Set up layer constraints properly for renderbuffersChris Forbes2014-05-091-10/+5
| | | | | | | | | | | Fixing the same issues the previous commit does for Gen7. Note that I can't test this one, since I don't have a Broadwell. V2: Restore the MAX2() to account for zero depth/layer_count. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen7: Set up layer constraints properly for renderbuffersChris Forbes2014-05-091-10/+7
| | | | | | | | | | | | | | | | There were a few problems here, which mostly just broke layered rendering into a view: - Render target view extent was always set to be == depth. This is benign for non-layered-rendering, but allows writes off the end of the render target for layered rendering, which ends badly. - Layered rendering did not honor the mt_layer setting, so would not properly handle MinLayer being set on a view. V2: Restore the MAX2() to account for zero depth/layer_count. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix typo in assert messageChris Forbes2014-05-091-1/+1
| | | | Signed-off-by: Chris Forbes <[email protected]>
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