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* i965: implement querying __DRI_IMAGE_ATTRIB_OFFSET.Chuanbo Weng2016-09-211-2/+7
| | | | | | | | | Implement querying this attribute in intelImageExtension and bump version of intelImageExtension. Signed-off-by: Chuanbo Weng <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* egl: return corresponding offset of EGLImage instead of 0.Chuanbo Weng2016-09-211-2/+9
| | | | | | | | | | | | | | | | | | The offset should not always be 0. For example, if EGLImage is created from a 2D texture with EGL_GL_TEXTURE_LEVEL=1, then the offset should be the actual start of miplevel 1 in bo. v2: Add version check of __DRIimageExtension implementation (Suggested by Axel Davy). v3: Don't add version check of __DRIimageExtension implementation. Set the offset only when queryImage() succeeds. (Suggested by Emil Velikov) Signed-off-by: Chuanbo Weng <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> [Emil Velikov: coding style fixes] Signed-off-by: Emil Velikov <[email protected]>
* i965/ir: Test thread dispatch packing assumptions.Francisco Jerez2016-09-211-0/+30
| | | | | | | | | | | | | | | | Not [originally] intended for upstream. Should cause a GPU hang if some thread is executed with a non-contiguous dispatch mask breaking assumptions of brw_stage_has_packed_dispatch(). Doesn't cause any CTS, DEQP or Piglit regressions, while replacing brw_stage_has_packed_dispatch() with a dummy implementation that unconditionally returns true on top of this patch causes multiple GPU hangs. v2: Refactor into a separate function instead of emitting the test code directly from emit_nir_code(), drop VEC4 test and clean up slightly for upstream. (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965/ir: Pass identity mask to brw_find_live_channel() in the packed ↵Francisco Jerez2016-09-212-3/+11
| | | | | | | | | dispatch case. This avoids emitting a few extra instructions required to take the dispatch mask into account when it's known to be tightly packed. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/ir: Skip eliminate_find_live_channel() for stages with sparse thread ↵Francisco Jerez2016-09-213-0/+65
| | | | | | | | | | | | | | | | | | dispatch. The eliminate_find_live_channel optimization eliminates FIND_LIVE_CHANNEL instructions in cases where control flow is known to be uniform, and replaces them with 'MOV 0', which in turn unblocks subsequent elimination of the BROADCAST instruction frequently used on the result of FIND_LIVE_CHANNEL. This is however not correct in per-sample fragment shader dispatch because the PSD can dispatch a fully unlit sample under certain conditions. Disable the optimization in that case. Reviewed-by: Jason Ekstrand <[email protected]> v2: Add devinfo argument to brw_stage_has_packed_dispatch() to implement hardware generation check.
* i965/fs: Take Dispatch/Vector mask into account in FIND_LIVE_CHANNELJason Ekstrand2016-09-215-13/+50
| | | | | | | | | | | | | | | | | | | On at least Sky Lake, ce0 does not contain the full story as far as enabled channels goes. It is possible to have completely disabled channels where the corresponding bits in ce0 are 1. In order to get the correct execution mask, you have to mask off those channels which were disabled from the beginning by taking the AND of ce0 with either sr0.2 or sr0.3 depending on the shader stage. Failure to do so can result in FIND_LIVE_CHANNEL returning a completely dead channel. Signed-off-by: Jason Ekstrand <[email protected]> Cc: Francisco Jerez <[email protected]> [ Francisco Jerez: Fix a couple of typos, add mask register type assertion, clarify reason why ce0 can have bits set for disabled channels, clarify that this may only be a problem when thread dispatch doesn't pack channels tightly in the SIMD thread. Apply same treatment to Align16 path. ] Reviewed-by: Francisco Jerez <[email protected]>
* i965/reg: Make brw_sr0_reg take a subnr and return a vec1 regJason Ekstrand2016-09-212-13/+9
| | | | | | | | | | | The state register sr0 is really a collection of dwords not a SIMD8 anything. It's much more convenient for brw_sr0_reg to return the particular dword you're looking for rather than a giant blob you have to massage into what you want. Signed-off-by: Jason Ekstrand <[email protected]> [ Francisco Jerez: Trivial simplification of brw_ud1_reg(). ] Reviewed-by: Francisco Jerez <[email protected]>
* anv: pipeline: use correct number of thread for computeLionel Landwerlin2016-09-211-1/+4
| | | | | | | | | | | | | Reproduces this commit : commit 0fb85ac08d61d365e67c8f79d6955e9f89543560 Author: Kenneth Graunke <[email protected]> Date: Mon Jun 6 21:37:34 2016 -0700 i965: Use the correct number of threads for compute shaders. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: allocator: correct scratch space for haswellLionel Landwerlin2016-09-211-1/+21
| | | | | | | | | | | | | This reproduces this commit : commit 2213ffdb4bb79856f0556bdf2bfd4bdf57720232 Author: Kenneth Graunke <[email protected]> Date: Mon Jun 6 21:37:34 2016 -0700 i965: Allocate scratch space for the maximum number of compute threads. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: device: calculate compute thread numbers using subslices numbersLionel Landwerlin2016-09-216-18/+74
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallivm: support negation on 64-bit integersNicolai Hähnle2016-09-211-0/+4
| | | | | | | This should be analogous to 32-bit integers. Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* radeonsi: prepare 64-bit integer support. (v2)Dave Airlie2016-09-211-7/+62
| | | | | | | | | | | v2: - no PIPE_CAP_INT64 yet - emit DIV/MOD without the divide-by-zero workaround Reviewed-by: Marek Olšák <[email protected]> (v1) Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* gallivm/llvmpipe: prepare support for ARB_gpu_shader_int64.Dave Airlie2016-09-215-5/+500
| | | | | | | | | | | | | | | | This enables 64-bit integer support in gallivm and llvmpipe. v2: add conversion opcodes. v3: - PIPE_CAP_INT64 is not there yet - restrict DIV/MOD defaults to the CPU, as for 32 bits - TGSI_OPCODE_I2U64 becomes TGSI_OPCODE_U2I64 Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* tgsi/softpipe: prepare ARB_gpu_shader_int64 support. (v3)Dave Airlie2016-09-211-132/+541
| | | | | | | | | | | | | | This adds all the opcodes to tgsi_exec for softpipe to use. v2: add conversion opcodes. v3: - no PIPE_CAP_INT64 yet - change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64 Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* gallium/tgsi: add support for 64-bit integer immediates.Dave Airlie2016-09-217-2/+117
| | | | | | | | | | This adds support to TGSI for 64-bit integer immediates. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: add opcode and types for 64-bit integers. (v3)Dave Airlie2016-09-214-20/+362
| | | | | | | | | | | | | | | | | This just adds the basic support for 64-bit opcodes, and the new types. v2: add conversion opcodes. add documentation. v3: - make docs more consistent - change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64 Reviewed-by: Marek Olšák <[email protected]> (v2) Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-2028-170/+170
| | | | | | | | "intelScreen" is wordy and also doesn't fit our style guidelines. "screen" is shorter, which is nice, because we use it fairly often. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Rename __DRIScreen pointers to "dri_screen".Kenneth Graunke2016-09-206-83/+85
| | | | | | | | | | | | | | | | I want to use "screen" as the variable name for a struct intel_screen pointer. This means that we can't use it for __DRIscreen pointers. Sometimes we called it "screen", sometimes "sPriv", sometimes "driScrnPriv", and sometimes "psp" (Pointer to Screen Private?). The last one is particularly confusing because we use "psp" to refer to the Gen4 PIPELINED_STATE_POINTERS packet as well. Let's be consistent. "dri_screen" is clear, and it's not used often enough that I'm worried about the verbosity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: Implement ARB_shader_viewport_layer_array for i965Dylan Baker2016-09-206-2/+18
| | | | | | | | | | | | | This extension is a combination of AMD_vertex_shader_viewport_index and AMD_vertex_shader_layer, making it rather trivial to implement. For gallium I *think* this needs a new cap because of the addition of support in tessellation evaluation shaders, and since I don't have any hardware to test it on, I've left that for someone else to wire up. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeon/vce: add firmware support for version 52.8.3Leo Liu2016-09-201-0/+3
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/omx/dec/h265: Correct the timestampingIndrajit Das2016-09-201-1/+12
| | | | | | | | | | | (derived from commit 3b6bda665a5a890f2c98e19d2939d7de92b8cb4c) v2: fix the tabs(Leo) Reviewed-by: Christian König <[email protected]> Reviewed-by: Nishanth Peethambaran <[email protected]> Signed-off-by: Indrajit Das <[email protected]> Signed-off-by: Leo Liu <[email protected]>
* aubinator: add a custom handler for immediate register loadLionel Landwerlin2016-09-203-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Transforming this : 0x00c77084: 0x11000001: MI_LOAD_REGISTER_IMM 0x00c77088: 0x0000b020 : Dword 1 Register Offset: 0x0000b020 0x00c7708c: 0x00880038 : Dword 2 Data DWord: 8912952 Into this: 0x007880f0: 0x11000001: MI_LOAD_REGISTER_IMM 0x007880f4: 0x0000b020 : Dword 1 Register Offset: 0x0000b020 0x007880f8: 0x00080040 : Dword 2 Data DWord: 524352 register L3CNTLREG2 (0xb020) : 0x80040 SLM Enable: 0 URB Allocation: 32 URB Low Bandwidth: 0 RO Allocation: 32 RO Low Bandwidth: 0 DC Allocation: 0 DC Low Bandwidth: 0 v2: Drop unused arguments (Sirisha) Print out register name Signed-off-by: Lionel Landwerlin <[email protected]>
* st/va: flush the context before calling flush_frontbuffer(v2)Nayan Deshmukh2016-09-201-1/+5
| | | | | | | | | | | | so that the texture is rendered to back buffer before calling flush_frontbuffer and can be copied to a different buffer in the function v2: change comment style Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Acked-by: Christian König <[email protected]>
* st/vdpau: flush the context before calling flush_frontbufferNayan Deshmukh2016-09-201-2/+5
| | | | | | | | | | so that the texture is rendered to back buffer before calling flush_frontbuffer and can be copied to a different buffer in the function Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Acked-by: Christian König <[email protected]>
* vl/dri3: handle the case of different GPU(v4.2)Nayan Deshmukh2016-09-201-13/+53
| | | | | | | | | | | | | | | | | | | In case of prime when rendering is done on GPU other then the server GPU, use a seprate linear buffer for each back buffer which will be displayed using present extension. v2: Use a seprate linear buffer for each back buffer (Michel) v3: Change variable names and fix coding style (Leo and Emil) v4: Use PIPE_BIND_SAMPLER_VIEW for back buffer in case when a seprate linear buffer is used (Michel) v4.1: remove empty line v4.2: destroy the context and handle the case when create_context fails (Emil) Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Leo Liu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Acked-by: Christian König <[email protected]>
* st/vdpau: fix argument type to vlVdpOutputSurfaceDMABufIlia Mirkin2016-09-202-2/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christian König <[email protected]>
* swr: [rasterizer core] Better thread destructionTim Rowley2016-09-198-69/+126
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] Fix missing end-of-file newlineTim Rowley2016-09-191-1/+2
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] Add macros for mapping ArchRast to bucketsTim Rowley2016-09-1911-200/+249
| | | | | | Switch all RDTSC_START/STOP macros to use AR_BEGIN/END macros. Signed-off-by: Tim Rowley <[email protected]>
* glsl: Skip "unsized arrays aren't allowed" check for TCS/TES/GS vars.Kenneth Graunke2016-09-191-1/+27
| | | | | | | | Fixes ESEXT-CTS.draw_elements_base_vertex_tests.AEP_shader_stages and ESEXT-CTS.texture_cube_map_array.texture_size_tesselation_con_sh. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: get rid of nvc0_stage_sampler_states_bind_range()Samuel Pitoiset2016-09-191-74/+9
| | | | | | | Same thing as nvc0_stage_set_sampler_views_range(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: get rid of nvc0_stage_set_sampler_views_range()Samuel Pitoiset2016-09-191-89/+15
| | | | | | | | This function was quite similar to nvc0_stage_set_sampler_views() and I don't see any reasons to not remove it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize SUB(a, b) to MOV(a - b)Samuel Pitoiset2016-09-181-0/+10
| | | | | | | | | | | | | | | | | | | This helps shaders in UE4 demos, especially with Elemental (+1% perf). This optimization reduces spilling usage in one shader which explains the little gain. GF100/GK104: total instructions in shared programs :2838551 -> 2838045 (-0.02%) total gprs used in shared programs :396706 -> 396684 (-0.01%) total local used in shared programs :34432 -> 34416 (-0.05%) local gpr inst bytes helped 1 19 112 112 hurt 0 0 0 0 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix wrong emission of OP_NOTSamuel Pitoiset2016-09-181-1/+1
| | | | | | | | | This should emit src0 instead of src1. Found by inspection. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* r600g/sb: fix struct/class declaration conflictsMartina Kollarova2016-09-181-5/+1
| | | | | | | | | A couple of forward-declarations were causing warnings in clang: 'value' defined as a class here but previously declared as a struct [-Wmismatched-tags] Signed-off-by: Martina Kollarova <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: Drop assertion about buffer offset at draw time.Eric Anholt2016-09-171-11/+0
| | | | | | | | | Given robust access, we should just be returning zeroes if the user gives us a base pointer that's too big, which is what was happens on a release build. This was caught by a webgl conformance test for out-of-bounds draws on servo. Reviewed-by: Kenneth Graunke <[email protected]>
* tgsi: Enable returns from within loopsLars Hamre2016-09-171-0/+4
| | | | | | | | Fixes the following piglit test (for softpipe): /spec/glsl-1.10/execution/fs-loop-return Signed-off-by: Lars Hamre <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: relax restriction of compressed formats for texture uploadCharmaine Lee2016-09-171-3/+22
| | | | | | | | | | | | | | | This patch relaxes the restriction of compressed formats for texture upload buffer. For now, 3D texture with compressed format is still not supported in the texture upload buffer path. As Brian noted, ETQW does many texture updates with glCompressedTexSubImage. This patch greatly improves the performance of the ETQW trace. Tested with ETQW, MTT piglit, glretrace, conform, viewperf v2: Per Brian's suggestion, removed the subregion boundary check. Reviewed-by: Brian Paul <[email protected]>
* svga: skip query flush if we already have the query resultBrian Paul2016-09-171-5/+5
| | | | | | | | | This reduces the number of times we flush in some situations (the arbocclude demo is one trivial example). Tested with Piglit, ETQW, Sauerbraten, arbocclude. Reviewed-by: Charmaine Lee <[email protected]>
* svga: remove unneeded svga_context_flush() in svga_end_query()Brian Paul2016-09-171-5/+0
| | | | | | | | | Since commit 99d8fe20abe1f we don't have to flush the command buffer when we end a query. Tested with Piglit, Sauerbraten, arbocclude, ETQW (noticably faster now). Reviewed-by: José Fonseca <[email protected]>
* svga: use upload buffer for upload texture.Charmaine Lee2016-09-176-26/+279
| | | | | | | | | | | | | With this patch, when running with vgpu10, instead of mapping directly to the guest backed memory for texture update, we'll use the texture upload buffer and use the transfer from buffer command to update the host side texture memory. This optimization yields about 20% performance improvement with Lightsmark2008 and about 40% with Tropics. Tested with Lightsmark2008, Tropics, Heaven, MTT piglit, glretrace, conform. Reviewed-by: Brian Paul <[email protected]>
* svga: refactor svga_texture_transfer_map/unmap functionsCharmaine Lee2016-09-171-217/+272
| | | | | | | | | Split the functions into separate functions for dma and direct map to make the code more readable. Tested with MTT piglit, glretrace, viewperf, conform, various OpenGL apps Reviewed-by: Brian Paul <[email protected]>
* svga: add SVGA3d_vgpu10_TransferFromBuffer()Charmaine Lee2016-09-173-0/+51
| | | | | | Also add the corresponding dump function to dump the TransferFromBuffer command. Reviewed-by: Brian Paul <[email protected]>
* svga: single sample surface can be created as non-multisamples surfaceCharmaine Lee2016-09-172-2/+6
| | | | | | | | | With this patch, single sample surface will be created as non-multisamples surface. Tested with piglit, glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: fix memory leak with sampler stateCharmaine Lee2016-09-171-3/+0
| | | | | | | | | | | This patch fixes a memory leak with sampler state when piglit is run with HW version 11. Sampler state clean up was incorrectly skipped in svga_cleanup_sampler_state() for vgpu9. Tested with piglit. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: fix prim type check/assignment in translate_indices()Brian Paul2016-09-171-2/+2
| | | | | | | | Left over test code spotted by Sinclair. Tested with piglit, Google Earth, Lightsmark, Heaven4, glretraces, etc. Reviewed-by: Sinclair Yeh <[email protected]>
* svga: use SVGA3D_QUERYTYPE_MAX for svga query type checkCharmaine Lee2016-09-171-3/+3
| | | | | | | | | Use SVGA3D_QUERYTYPE_MAX instead of SVGA_QUERY_MAX for svga query type check. Tested with various OpenGL apps with GALLIUM_HUD set. Reviewed-by: Brian Paul <[email protected]>
* svga: split the num-resources-mapped hud to textures & buffersCharmaine Lee2016-09-175-12/+26
| | | | | | | | Replace the num-resources-mapped hud with num-textures-mapped and num-buffers-mapped, so we can differentiate the map counts for these two different resources. Reviewed-by: Brian Paul <[email protected]>
* svga: change svga hud defines to enumsCharmaine Lee2016-09-171-22/+25
| | | | | | This will make it easier to add new hud types. Reviewed-by: Brian Paul <[email protected]>
* svga: implement an index buffer translation cacheBrian Paul2016-09-175-6/+84
| | | | | | | | | | | | | | | Some OpenGL apps, like Cinebench R15, have many glDrawElements(GL_QUADS) calls. Since we don't directly support quads we have to convert these calls into GL_TRIANGLES which involves generating a new index buffer. This patch saves the new/translated index buffer in the hope that it can be reused for a later draw call. Cinebench R15 increases by about 20% with this change. The NobelClinician Viewer app also hits this code. Tested with full piglit run. Reviewed-by: Charmaine Lee <[email protected]>
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