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* glsl: Fix indentation of switch code.Eric Anholt2012-05-171-282/+263
| | | | | | | I managed to completely trash it in 22d81f15. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vs: Fix up swizzle for dereference_array of matrices.Eric Anholt2012-05-171-2/+2
| | | | | | | | | Fixes assertion failure in piglit: vs-mat2-struct-assignment.shader_test vs-mat2-array-assignment.shader_test Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Throw error on glGetActiveUniform inside Begin/End.Eric Anholt2012-05-171-0/+2
| | | | | | | | Fixes piglit GL_ARB_shader_objeccts/getactiveuniform-beginend. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Improve the local dead code optimization to eliminate unused channels.Eric Anholt2012-05-171-23/+126
| | | | | | | | | | | | | | | Total instructions: 261582 -> 261316 135/2147 programs affected (6.3%) 36752 -> 36486 instructions in affected programs (0.7% reduction) This excludes a tropics shader that now gets 16-wide mode and throws off the numbers. 5 shaders are hurt: two extra MOVs in 4 tropics shaders it looks like because we don't split register names according to independent webs, and one gstreamer shader where it looks like try_rewrite_rhs_to_dst() is falling on its face. This should also help avoid a regression in VSes from idr's ARB programs to GLSL work.
* i965/fs: Do more register coalescing by using the interference graph.Eric Anholt2012-05-172-0/+62
| | | | | | | | | | | | | | By using the live variables code for determining interference, we can handle coalescing in the presence of control flow, which the other register coalescing path couldn't. Total instructions: 207184 -> 206990 74/1246 programs affected (5.9%) 33993 -> 33799 instructions in affected programs (0.6% reduction) There is a newerth shader that loses out, because of some extra MOVs that now get their dead-code nature obscured by coalescing. This should be fixed by doing better at dead code elimination.
* nouveau: place static buffers in VRAM if preferred by the driverChristoph Bumiller2012-05-176-12/+62
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* nv50/ir: fix reversed order of lane ops in quadopsChristoph Bumiller2012-05-172-4/+6
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* nv50,nvc0: handle user vertex buffersChristoph Bumiller2012-05-1714-308/+423
| | | | And restructure VBO validation a little in the process.
* nv50,nvc0: handle user index buffersChristoph Bumiller2012-05-178-47/+49
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* nv50,nvc0: handle user constbufs without wrapping them in a resourceChristoph Bumiller2012-05-1714-165/+201
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* st/mesa: set PIPE_BIND_STREAM_OUTPUT for TFB target in st_bufferobj_dataChristoph Bumiller2012-05-171-0/+3
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* darwin: Eliminate a possible race condition while destroying a surfaceJeremy Huddleston2012-05-161-4/+4
| | | | | Introduced by: c60ffd2840036af1ea6f2b6c6e1e9014bb8e2c34 Signed-off-by: Jeremy Huddleston <[email protected]>
* darwin: Unlock our mutex before destroying itJeremy Huddleston2012-05-161-0/+3
| | | | | | http://xquartz.macosforge.org/trac/ticket/575 Signed-off-by: Jeremy Huddleston <[email protected]>
* gallium/radeon: Fix r300g tiling breakage.Michel Dänzer2012-05-166-3/+18
| | | | | | Commit 11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 broke the r300g build. Fix it up, and reinstate some code which isn't needed by r600g and radeonsi but is by r300g.
* gallium/auxiliary/pipe-loader: Fix usage of anonymous union.Francisco Jerez2012-05-163-8/+8
| | | | | | | | | Anonymous unions aren't part of the C99 standard. Fixes build on GCC versions older than 4.6. https://bugs.freedesktop.org/show_bug.cgi?id=50001 Reported-by: Michael Lange <[email protected]>
* radeonsi: Initial tiling support.Michel Dänzer2012-05-167-131/+359
| | | | Largely based on the corresponding Evergreen support in r600g.
* r600g: Set tiling information for BOs being shared.Michel Dänzer2012-05-163-9/+47
| | | | Fixes https://bugs.freedesktop.org/show_bug.cgi?id=48747
* st/xorg: Better handling of EXA copies.Michel Dänzer2012-05-164-225/+41
| | | | | Always use the resource_copy_region hook. If a source and destination rectangle overlap, copy to/from a temporary pixmap.
* radeonsi: Bump MAX_DRAW_CS_DWORDS.Michel Dänzer2012-05-163-3/+3
| | | | I missed this when updating si_context_draw().
* draw,llvmpipe: Avoid named struct types on LLVM 3.0 and later.José Fonseca2012-05-162-30/+6
| | | | | | | | | | | | Starting with LLVM 3.0, named structures are meant not for debugging, but for recursive data types, previously also known as opaque types. The recursive nature of these types leads to several memory management difficulties. Given that we don't actually need recursive types, avoid them altogether. This is an attempt to address fdo bugs 41791 and 44466. The issue is somewhat random so there's no easy way to check how effective this is.
* llvmpipe: Color slot interpolation can be flat or perspective, not linear.Olivier Galibert2012-05-163-3/+3
| | | | | | | Fixes a bunch of glsl 1.10 interpolation piglit tests. Signed-off-by: Olivier Galibert <[email protected]> Signed-off-by: José Fonseca <[email protected]>
* gallivm: Add MCRegisterInfo.h to silence benign warnings about missing ↵José Fonseca2012-05-151-0/+3
| | | | | | implementation. Trivial.
* i965/blorp: Move exec() out of brw_blorp_params.Paul Berry2012-05-153-6/+9
| | | | | | | | | No functional change. This patch replaces the brw_blorp_params::exec() method with a global function brw_blorp_exec() that performs the operation described by the params data structure. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Initial implementation of MSAA.Paul Berry2012-05-1523-121/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to understand multisampled buffers, adapting the rendering pipeline setup to enable multisampled rendering, and adding multisample resolve operations to brw_blorp_blit.cpp. Some preparation work is also included for Gen7, but it is not yet enabled. MSAA support is still fairly preliminary. In particular, the following are not yet supported: - Fully general blits between MSAA and non-MSAA buffers. - Formats other than RGBA8, DEPTH24, and STENCIL8. - Centroid interpolation. - Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE, GL_SAMPLE_COVERAGE_INVERT). Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on i965/Gen6. v2: - In intel_alloc_renderbuffer_storage(), quantize the requested number of samples to the next higher sample count supported by the hardware. This ensures that a query of GL_SAMPLES will return the correct value. It also ensures that MSAA is fully disabled on Gen7 for now (since Gen7 MSAA support doesn't work yet). - When reading from a non-MSAA surface, ensure that s_is_zero is true so that we won't try to read from a nonexistent sample.
* i965/gen6+: Add code to perform blits on the render path ("blorp").Paul Berry2012-05-158-27/+1730
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch expands the "blorp" component to be able to perform blits as well as HiZ resolves. The new blitting code is located in brw_blorp_blit.cpp. This includes the necessary fragment shader code to look up pixels in the source buffer (which is configured as a texture) and output them to the destination buffer (which is configured as the render target). Most of the time the fragment shader code is simple and straightforward, since it merely has to apply a coordinate offset, read from the texture, and write to the render target. However, in the case of blitting stencil buffers, things are more complicated, since the GPU stores stencil data using W tiling, and W tiling is not supported for textures or render targets. So, we set up the stencil buffers as Y tiled, and emit fragment shader code that adjusts the coordinates to account for the difference between W and Y tiling. Furthermore, since a rectangular region in W tiling does not necessarily correspond to a rectangular region in Y tiling, we widen the rectangle primitive to the nearest tile boundary and have the fragment shader "kill" any pixels that don't fall inside the actual desired destination rectangle. All of this is a necessary prerequisite for implementing MSAA, since we'll need to be able to blit between multisample color, depth, and stencil buffers and their non-multisampled counterparts, and none of the existing blitting mechanisms support multisampling. In addition, the new blitting code should speed up operations where we previously fell back to software rasterization, such as blitting of stencil buffers. The current fallback sequence is: first we try to do a blit using the hardware blitting engine. If that fails we try to do a blit using the render path. If that also fails then we do the blit using a meta-op (which may or may not fall back to software rasterization). Note that blitting using the render path has some limitations at the moment: it only supports a few formats, and it doesn't support clipping or scissoring. These limitations will be addressed in future patch series. v2: - Add the code that configures the WM program to gen{6,7}_emit_wm_config() and gen7_emit_ps_config() rather than creating separate ...enable() functions. - Call intel_prepare_render before determining which miptrees we are blitting from/to, because it may cause miptrees to be reallocated. - Allow the blit to mirror X and/or Y coordinates. - Disable blorp blits on Gen7 for now, since they aren't working yet.
* i965: Expose surface setup internals for use by blits.Paul Berry2012-05-153-2/+4
| | | | | | | | This patch exposes the functions brw_get_surface_tiling_bits and gen7_set_surface_tiling, so that they can be re-used when setting up surface states in gen6_blorp.cpp and gen7_blorp.cpp. Reviewed-by: Chad Versace <[email protected]>
* i965: split gen{6,7}_blorp_exec functions into manageable chunks.Paul Berry2012-05-153-522/+647
| | | | | | | | | | | | | | | | | This patch splits up the gen6_blorp_exec and gen7_blorp_exec functions, which were very long, into simple component functions. With a few exceptions, there is one function per state packet. This will allow blit functionality to be added without significantly complicating the code. Reviewed-by: Chad Versace <[email protected]> v2: Rename the functions gen{6,7}_emit_wm_disable() to gen{6,7}_emit_wm_config() (since the WM is not actually disabled during HiZ ops; it simply doesn't have a program). Also, on gen7, split out the configration of 3DSTATE_PS to a separate function gen7_emit_ps_config().
* i965: Parameterize HiZ code to prepare for adding blitting.Paul Berry2012-05-157-177/+335
| | | | | | | | | | | | | | | | | | | This patch groups together the parameters used by the HiZ functions into a new data structure, brw_hiz_resolve_params, rather than passing each parameter individually between the HiZ functions. This data structure is a subclass of brw_blorp_params, which represents the parameters of a general-purpose blit or resolve operation. A future patch will add another subclass for blits. In addition, this patch generalizes the (width, height) parameters to a full rect (x0, y0, x1, y1), since blitting operations will need to be able to operate on arbitrary rectangles. Also, it renames several of the HiZ functions to reflect the expanded role they will serve. v2: Rename brw_hiz_resolve_params to brw_hiz_op_params. Move gen{6,7}_blorp_exec() functions back into gen{6,7}_blorp.h. Reviewed-by: Chad Versace <[email protected]>
* i965: Implement guardband clipping on Ivybridge.Kenneth Graunke2012-05-152-5/+15
| | | | | | | | | | | Improves performance in Citybench: - 320x240: 9.19589% +/- 0.557621% - 1280x480: 3.90797% +/- 0.774429% No apparent difference in OpenArena. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Implement guardband clipping on Sandybridge.Kenneth Graunke2012-05-152-10/+15
| | | | | | | | | | | Improves performance in Citybench: - 320x240: 19.8008% +/- 0.937818% - 1280x480: 6.53856% +/- 0.859083% No apparent difference in OpenArena nor Xonotic. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* llvmpipe: Add a test for lp_build_sgn.José Fonseca2012-05-151-0/+13
| | | | Only floating point though, but better than nothing.
* gallivm: Fix lp_build_sgn for normalized/fixed-point integers.José Fonseca2012-05-151-1/+2
| | | | | These types got broken with the recent commit that fixed lp_build_sgn for negative integers.
* gallivm: Fix lp_build_const_xxx for negative integers.José Fonseca2012-05-151-5/+6
| | | | | | Do proper rounding. Thanks to Olivier Galibert for investigating this.
* svga: fix FBO / viewport bugsBrian Paul2012-05-151-7/+24
| | | | | | | | | | | When drawing to a FBO, the viewport wasn't always set correctly. It was fine in the usual case of the viewport dims matching the surface dims but broken otherwise. In particular, this was happening because the viewport scale is negative for FBO rendering. The piglit fbo-viewport test exercises this. Reviewed-by: José Fonseca <[email protected]>
* radeon/llvm: add support for texture offsets, fix TEX_LDVadim Girlin2012-05-154-10/+51
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_GVadim Girlin2012-05-156-9/+108
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: increase const regs countVadim Girlin2012-05-151-1/+1
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use IntrNoMem property for intrinsics where possibleVadim Girlin2012-05-157-105/+171
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: use correct intrinsic for CEILVadim Girlin2012-05-152-3/+3
| | | | | | | Should be round_posinf instead of round_neginf. Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: improve ABS_i32 loweringVadim Girlin2012-05-151-13/+5
| | | | | | | | | We can save one instruction by lowering it to: SUB_INT tmp, 0, src MAX_INT dst, src, tmp Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: fix BUILD_VECTOR lowering for replicated valueVadim Girlin2012-05-151-0/+2
| | | | | | | We expect that all elements will be assigned even if they are equal Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add names for AMDGPU* passesVadim Girlin2012-05-152-0/+5
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: add generated files to .gitignoreVadim Girlin2012-05-151-0/+18
| | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* Add .gitignore files for recently-added gallium projectsPaul Berry2012-05-153-0/+3
| | | | | | | This patch adds .gitignore files to ignore the makefiles generated by the gallium pipe loader and the clover OpenCL state tracker. Reviewed-by: Francisco Jerez <[email protected]>
* glsl: Fix lower_discard_flow prototype mismatch.José Fonseca2012-05-151-1/+1
| | | | Should fix MSVC link failure.
* Revert "i965/fs: Jump from discard statements to the end of the program when ↵Eric Anholt2012-05-144-126/+5
| | | | | | | | | | done." This reverts commit 31866308fcf989df992ace28b5b986c3d3770e90. Fixes piglit glsl-fs-discard-exit-3 and unigine tropics rendering. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Implement the GLSL 1.30+ discard control flow rule in GLSL IR.Eric Anholt2012-05-144-0/+157
| | | | | | | Previously, I tried implementing this in the i965 driver, but did so in a way that violated the intent of the spec, and broke Tropics. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Remove the opt_discard_simplification pass.Eric Anholt2012-05-144-209/+0
| | | | | | | This conflicts with the GLSL 1.30+ rules for derivatives after a discard has occurred. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove the requirement of no dead code for interference checks.Eric Anholt2012-05-141-12/+12
| | | | | | | | This will be convenient when I want to comment out optimization code to see the raw program being optimized, but more importantly will let the interference check be used during optimization. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for copy propagation.Eric Anholt2012-05-145-0/+143
| | | | | | | | | | | | We could do more by handling abs/negate and non-GRF sources, but this is a good start. Improves tropics performance 0.30% +/- .17% (n=43). shader-db results: Total instructions: 208032 -> 207184 60/1246 programs affected (4.8%) 23286 -> 22438 instructions in affected programs (3.6% reduction) Reviewed-by: Kenneth Graunke <[email protected]>
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