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* gallium/vl: use the common uploaderMarek Olšák2017-02-143-17/+2
| | | | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* gallium/vbuf: use the common uploaderMarek Olšák2017-02-141-10/+4
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* gallium/blitter: use the common uploaderMarek Olšák2017-02-141-9/+3
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* gallium/primconvert: use the common uploaderMarek Olšák2017-02-141-10/+2
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* gallium/hud: use the common uploaderMarek Olšák2017-02-141-9/+2
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* gallium: set pipe_context uploaders in drivers (v3)Marek Olšák2017-02-1418-6/+131
| | | | | | | | | | | | | | | Notes: - make sure the default size is large enough to handle all state trackers - pipe wrappers don't receive transfer calls from stream_uploader, because pipe_context::stream_uploader points directly to the underlying driver's stream_uploader (to keep it simple for now) v2: add error handling to nv50, nvc0, noop v3: set const_uploader Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> (v1) Tested-by: Charmaine Lee <[email protected]>
* gallium/u_upload_mgr: add a helper that creates the default uploaderMarek Olšák2017-02-142-0/+16
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* gallium: add common uploaders into pipe_context (v2)Marek Olšák2017-02-142-0/+34
| | | | | | | | | | | | For lower memory usage and more efficient updates of the buffer residency list. (e.g. if drivers keep seeing the same buffer for many consecutive "add" calls, the calls can be turned into no-ops trivially) v2: add const_uploader, add documentation Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* radv: fixup IA_MULTI_VGT_PARAM handling.Dave Airlie2017-02-144-31/+105
| | | | | | | | | This ports the remains of the workarounds from radeonsi for the non-TESS cases. It should provide equivalent workarounds for hawaii and bonarie. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix warning since using common gs emit codeDave Airlie2017-02-141-1/+0
| | | | Signed-off-by: Dave Airlie <[email protected]>
* radv: adopt some init config workarounds from radeonsi.Dave Airlie2017-02-151-2/+9
| | | | | | | | | Just one bonaire fix. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0 17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: re-enable init gfx state on CIK.Dave Airlie2017-02-151-2/+1
| | | | | | | | | Once the color alignment was fixed this works fine now. Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: align the initial state command buffer.Dave Airlie2017-02-151-0/+7
| | | | | | | | | This just adds the padding to align this to an 8 dword boundary. Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix cik macroModeIndex.Dave Airlie2017-02-151-0/+14
| | | | | | | | | | This just a CIK fix ported from radeonsi. Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0 17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: change base aligmment for allocated memory.Dave Airlie2017-02-151-1/+1
| | | | | | | | | | | | | | | On some CIK (Hawaii) this needs to be at least 64k, I'm not 100% sure it doesn't need to be 128k. This was causing fast clear eliminate to overwrite the previous buffer, which since my gfx init code, was the indirect buffer. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99692 Tested-by: Kai Wasserbäch <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0 17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* anv: Add support for shaderStorageImageWriteWithoutFormatAlex Smith2017-02-146-23/+65
| | | | | | | | | | | | | | | | | | | | | | This allows shaders to write to storage images declared with unknown format if they are decorated with NonReadable ("writeonly" in GLSL). Previously an image view would always use a lowered format for its surface state, however when a shader declares a write-only image, we should use the real format. Since we don't know at view creation time whether it will be used with only write-only images in shaders, create two surface states using both the original format and the lowered format. When emitting the binding table, choose between the states based on whether the image is declared write-only in the shader. Tested on both Sascha Willems' computeshader sample (with the original shaders and ones modified to declare images writeonly and omit their format qualifiers) and on our own shaders for which we need support for this. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add support for SpvCapabilityStorageImageWriteWithoutFormatAlex Smith2017-02-143-2/+9
| | | | | | | | | | | Allow that capability if the driver indicates that it is supported, and flag whether images are read-only/write-only in the nir_variable (based on the NonReadable and NonWritable decorations), which drivers may need to implement this. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/spirv: do not require a format with images that are not sampledIago Toral Quiroga2017-02-141-2/+0
| | | | | | | As soon as we support shaderStorageImageWriteWithoutFormat we can see write-only images (sampled == 2) that don't have a format specified. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/apply_pipeline_layout: Set image.write_only to falseJason Ekstrand2017-02-141-0/+12
| | | | | | | | | | This makes our driver robust to changes in spirv_to_nir which would set this flag on the variable. Right now, our driver relies on spirv_to_nir *not* setting var->data.image.write_only for correctness. Any patch which implements the shaderStorageImageWriteWithoutFormat will need to effectively revert this commit. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add format metadata for typed reads/writesJason Ekstrand2017-02-142-251/+291
| | | | | | | | This adds two columns to the format table as well as two helpers for determining whether or not a given format is supported for typed reads and writes. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/cmd_buffer: Return a VkResult from verify_cmd_parserJason Ekstrand2017-02-141-7/+7
| | | | | | This fixes a "statement with no effect" compiler warning Reviewed-by: Lionel Landwerlin <[email protected]>
* nvc0: disable linked tsc mode in compute launch descriptorIlia Mirkin2017-02-132-2/+6
| | | | | | | | | | Empirically, this makes things work. Presumably this was originally copied from the blob, which does make use of linked tsc mode. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99532 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* mesa: Add EXT_frag_depth bits and enable it on all driversAnuj Phogat2017-02-134-0/+7
| | | | | | | | | Passes the newly added piglit test for this extension on i965. V2: Fix comments by Ilia. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: use common sendmsg emission function.Dave Airlie2017-02-141-26/+6
| | | | | | | | This just ports radeonsi to use the sendmsg common code. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: use sendmsg emission interface.Dave Airlie2017-02-141-26/+4
| | | | | | | This uses the common code to emit the correct intrinsic. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon/ac/llvm: add support for sendmsg emissionDave Airlie2017-02-142-0/+25
| | | | | | | | | This lets us use the new intrinsic on the correct version of llvm. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: disable gfx init on CIK for nowDave Airlie2017-02-141-1/+2
| | | | | | | Luzipher on irc report this hangs his Hawaii, disable for now until I get time to debug. Signed-off-by: Dave Airlie <[email protected]>
* tgsi: fix memory leak in tgsi sanity checkDave Airlie2017-02-141-3/+5
| | | | | | | | | This just fixes this without repeating the code. Reported-by: Li Qiang Cc: "17.0" <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: use common interp code for new intrinsicsDave Airlie2017-02-141-20/+41
| | | | | | | | This uses the common fs interp code to use the new llvm intrinsics so llvm can drop the old ones. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use indirect buffer for initial gfx state.Dave Airlie2017-02-134-1/+62
| | | | | | | | | | This puts the common gfx state for the device into an indirect buffer, and just calls out to it, on CIK and above. This is taken from what radeonsi does. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: start splitting init config upDave Airlie2017-02-131-8/+20
| | | | | | | | This is just prep work for the following patch to use a common gfx init indirect buffer. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: don't pass physical device to si_init_ fns.Dave Airlie2017-02-133-11/+9
| | | | | | | This is just a trivial cleanup. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: detect command buffers that do no work and drop them (v2)Dave Airlie2017-02-135-8/+27
| | | | | | | | | | | | | | If a buffer is just full of flushes we flush things on command buffer submission, so don't bother submitting these. This will reduce some CPU overhead on dota2, which submits a fair few command streams that don't end up drawing anything. v2: reorganise loop to count first then malloc, rename some vars (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* anv/blorp: Don't sanitize the swizzle for blorp_clearJason Ekstrand2017-02-131-2/+1
| | | | | | | | | | | | | BLORP is now smart enough to handle any swizzle (even those that contain ZERO or ONE) in a reasonable manner. Just let BLORP handle it. This fixes the following Vulkan CTS tests on Haswell: - dEQP-VK.api.image_clearing.clear_color_image.1d_b4g4r4a4_unorm_pack16 - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16 - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16 Reviewed-by: Juan A. Suarez Romero <[email protected]> Cc: "17.0" <[email protected]>
* intel/blorp: Swizzle clear colors on the CPUJason Ekstrand2017-02-131-18/+30
| | | | | | | | | It's trivial to swizzle clear colors on the CPU, easily deals with the hardware restrictions for render target swizzles, and makes swizzled clears work on all hardware as opposed to just HSW+. Reviewed-by: Juan A. Suarez Romero <[email protected]> Cc: "17.0" <[email protected]>
* st/xlib: remove always true ifdef GLX_EXTENSION guardsEmil Velikov2017-02-131-6/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]>
* xlib: remove always true ifdef GLX_EXTENSION guardsEmil Velikov2017-02-132-26/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]>
* glx: remove always true XDAMAGE_1_1_INTERFACE guardEmil Velikov2017-02-131-4/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glx: remove DRI2DriverPrimeShift compile guardsEmil Velikov2017-02-131-2/+0
| | | | | | | | DRI2DriverPrimeShift was added in dri2proto-2.8, which we now require as of the previous commit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* vl: remove DRI2DriverPrimeShift compile guardsEmil Velikov2017-02-131-2/+0
| | | | | | | | DRI2DriverPrimeShift was added in dri2proto-2.8, which we now require as of the previous commit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glx: remove always true ifdef guardsEmil Velikov2017-02-131-4/+0
| | | | | | | | The two symbols referenced were introduced with v2.2 and 2.3 of the dri2proto package and we require dri2proto >= 2.6. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* winsys/intel: remove unused winsys - ilo was its only userEmil Velikov2017-02-135-744/+0
| | | | | Cc: Edward O'Callaghan <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* util/disk_cache: correctly use stat(3)Timothy Arceri2017-02-131-4/+4
| | | | | | | | | I forgot to error check stat() and also I wasn't using the subdir in is_two_character_sub_directory(). Fixes: d7b3707c612 "util/disk_cache: use stat() to check if entry is a directory" Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl: Drop resize-to-MaxPatchVertices hack.Kenneth Graunke2017-02-124-43/+0
| | | | | | | | | | | | | | TCS and TES inputs without an array size are implicitly sized to gl_MaxPatchVertices. But TCS outputs are apparently not: "If no size is specified, it will be taken from the output patch size (gl_VerticesOut) declared in the shader." Fixes dEQP-GLES31.functional.program_interface_query.program_output. array_size.separable_tess_ctrl.var. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* mesa: Ignore per-vertex array size in SSO pipeline validation.Kenneth Graunke2017-02-121-42/+56
| | | | | | | | | | | | We were already unwrapping types when the producer was a non-array stage and the consumer was an arrayed-stage...but we ought to unwrap both ends for TCS -> TES matching too. This will allow us to drop the "resize to gl_MaxPatchVertices" check shortly, which breaks some things. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl: Update a comment about link errors for TCS && !TES.Kenneth Graunke2017-02-121-1/+9
| | | | | | | | OpenGL ES actually has spec text to prohibit this. It's just OpenGL that's confusing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* mesa: Do a draw time check for TES && !TCS in ES 3.x.Kenneth Graunke2017-02-121-0/+14
| | | | | | | | | | | | | ES 3.x requires both TCS and TES to be present. We already checked the TCS && !TES case above, so we just have to check !TCS && TES here. Note that this is allowed in OpenGL, just not ES. This fixes a subcase of: dEQP-GLES31.functional.debug.negative_coverage.*.tessellation.single_tessellation_stage Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* mesa: Do (TCS && !TES) draw time validation in ES as well.Kenneth Graunke2017-02-121-19/+26
| | | | | | | | | | | | | | | | | Now that we have OES_tessellation_shader, the same situation can occur in ES too, not just GL core profile. Having a TCS but no TES may confuse drivers - i965 crashes, for example. This prevents regressions in ES31-CTS.core.tessellation_shader.single.xfb_captures_data_from_correct_stage with some SSO pipeline validation changes I'm making. v2: Add an ES spec citation (suggested by Alejandro) Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965/sampler_state: Set the "Base Mip Level" field on Sandy BridgeJason Ekstrand2017-02-122-1/+20
| | | | | | | | | | | Fixes two GL ES 3.0 CTS tests on Sandy Bridge: ES3-CTS.functional.texture.mipmap.cube.base_level.linear_linear ES3-CTS.functional.texture.mipmap.cube.base_level.linear_nearest Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.0 13.0" <[email protected]>
* i965/sampler_state: Pass texObj into update_sampler_stateJason Ekstrand2017-02-121-6/+4
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.0 13.0" <[email protected]>
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