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* radv: use vk_error() everywhere an error is returnedSamuel Pitoiset2017-11-138-27/+27
| | | | | | | For consistency and it might help for debugging purposes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make radv_emit_framebuffer_state() staticSamuel Pitoiset2017-11-132-3/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not emit the framebuffer when restoring a passSamuel Pitoiset2017-11-131-1/+1
| | | | | | | | Instead just dirty RADV_CMD_DIRTY_FRAMEBUFFER and it will be re-emitted if necessary before the next draw. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: prefetch VBO descriptors at the right placeSamuel Pitoiset2017-11-132-0/+21
| | | | | | | | | | | Just after the vertex shader. This seems to give a minor boost for, at least, Serious Sam Fusion 2017 and Dawn of War 3. I don't see any real impacts with The Talos Principle. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_emit_prefetch_TC_L2_async() helperSamuel Pitoiset2017-11-131-2/+9
| | | | | | | Will be used for VBO descriptors prefetching. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename radv_emit_shaders_prefetch() to radv_emit_prefetch()Samuel Pitoiset2017-11-131-6/+6
| | | | | | | | For consistency because this function will also prefetch VBO descriptors. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl/linker: use without_array() to retrieve typeIago Toral Quiroga2017-11-131-3/+4
| | | | | | | | This is what we do in the condition too, so it makes sense. v2: Only compute without_array() once (Ilia). Reviewed-by: Ilia Mirkin <[email protected]>
* radv: emit esgs ring size in one place.Dave Airlie2017-11-132-7/+8
| | | | | | | | | This register is the same on all gpus so far, so emit it in one place and also for the pre-gfx9 gpus set the value in the pipeline creation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating vs out info regs into pipeline.Dave Airlie2017-11-133-25/+34
| | | | | | | | This moves some calculations of register values into the pipeline construction, it saves looking at outinfo in the cmd buffer emit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/a5xx: fix SSBO emit for non-zero offsetRob Clark2017-11-121-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove obsolete commentRob Clark2017-11-121-4/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't create split/fo if only writing .xRob Clark2017-11-121-0/+6
| | | | | | | In case an instruction only writes one register, and it is .x, we can skip the extra level of fanout indirection. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: indirect gridsRob Clark2017-11-123-20/+86
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add global size compute capRob Clark2017-11-121-0/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: turn on std430 packingRob Clark2017-11-121-1/+6
| | | | | | Seems to fix dEQP compute related tests.. and matches what i965 does, so perhaps there is some assumption that std430 packing is on by default somewhere in NIR?
* freedreno/a5xx: image supportRob Clark2017-11-128-31/+306
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* freedreno/ir3: moar better schedulerRob Clark2017-11-125-58/+227
| | | | | | | | | | | | | | | | | | Add a new pass that inserts additional dependencies, rather than simply relying on SSA srcs added in the nir->ir3 frontend. This makes it easier to deal with barriers, but the additional false deps also lets us deal properly with ensuring a write depends on all previous reads. Since conversion to barrier instructions is lossy (ie. just knowing the instruction doesn't tell us enough about what other instructions the barrier applies to), use barrier_class/barrier_conflict fields in the ir3_instruction to retain this information. This could probably be relaxed somewhat by considering *which* array/ buffer/image variable is being referenced. Ie. a write to buffer A can overtake a read from buffer B, if B is not coherent. (right?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move macrosRob Clark2017-11-121-15/+15
| | | | | | | | | | I want to add a growable array to ir3_instruction, so we can append false dependencies for purposes of scheduling barriers, atomics, and dealing with write after read hazards. Just code motion preparing for next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: image supportRob Clark2017-11-125-0/+337
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shared variable supportRob Clark2017-11-123-2/+177
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: some SSBO cleanups/fixesRob Clark2017-11-122-15/+39
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out INSTR4F instructionsRob Clark2017-11-122-29/+64
| | | | | | | | Atomic instructions take a different # of src args depending on .g or .l variant, split these out into different helpers with INSTR*F() helper macro that lets you specify instruction flag. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cat6 encoding fixesRob Clark2017-11-124-32/+151
| | | | | | | Instruction encoding/decoding fixes needed for images, shared variables, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add barriersRob Clark2017-11-122-0/+55
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: invert is_same_type_mov() logicRob Clark2017-11-121-10/+16
| | | | | | | | Some instructions (like barriers) have no dst, which causes problems with dereferencing a NULL dst. Flip the logic around to reject opc's that can't be a type of move first, to filter out those instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add cat7 instructionsRob Clark2017-11-124-2/+79
| | | | | | Needed for memory and execution barriers. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add SSBO get_buffer_size() supportRob Clark2017-11-126-11/+122
| | | | | | Somehow I overlooked this when adding initial SSBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: extract helper for common constsRob Clark2017-11-121-34/+17
| | | | | | | | User consts and driver consts such as UBO addresses and immediates are handled the same for all shader stages, so split out a shared helper for these, to make it easier to add more. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add image view state trackingRob Clark2017-11-122-0/+56
| | | | | | | | | It is unfortunate that image state isn't a real CSO, since (at least for a4xx/a5xx) it is a combination of sampler and "SSBO" image state, and it would be useful to pre-compute the state block "register" values rather than doing it at emit time. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-11-126-19/+142
| | | | Signed-off-by: Rob Clark <[email protected]>
* mesa/st/nir: assign driver_location for imagesRob Clark2017-11-121-2/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* st/program: fix compute shader nir referencesRob Clark2017-11-122-6/+24
| | | | | | | | | | | In case the IR is NIR, the driver takes reference to the nir_shader. Also, because there are no variants, we need to clone the shader, instead of sharing the reference with gl_program, which would result in a double free in _mesa_delete_program(). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* freedreno/ir3: rename ir3_compile -> ir3_contextRob Clark2017-11-121-57/+57
| | | | | | | | | Having both an ir3_compile (which was really context for compiling a single shader variant) and ir3_compiler (which is the compiler object that compiles all variants, ie. basically holds the RA regset) is a bit confusing. Signed-off-by: Rob Clark <[email protected]>
* intel/tools: Fix detection of enabled shader stages.Kenneth Graunke2017-11-121-1/+1
| | | | | | | | | | We renamed "Function Enable" to "Enable", which broke our detection of whether shaders are enabled or not. So, we'd see a bunch of HS/DS packets with program offsets of 0, and think that was a valid TCS/TES. Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".) Reviewed-by: Lionel Landwerlin <[email protected]>
* st/atifs: remove unrequired initialisation of gl_program fieldsTimothy Arceri2017-11-121-4/+0
| | | | | | | | As far as I can tell these fields are only used to query arb program info and are not related to ATI_fragment_shader. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Miklós Máté <[email protected]>
* ac: add emit_vertex to the abiTimothy Arceri2017-11-123-19/+31
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rework gs_vtx_offset handlingTimothy Arceri2017-11-122-22/+10
| | | | | | | This simplifies things a bit and will enable it to work with the common NIR -> LLVM code. Reviewed-by: Marek Olšák <[email protected]>
* nir: add streams to nir dataTimothy Arceri2017-11-122-0/+9
| | | | | | This will be used by gallium drivers. Reviewed-by: Marek Olšák <[email protected]>
* st/dri: fix deadlock when waiting on android fencesMarek Olšák2017-11-113-6/+2
| | | | | | | Android fences can't be deferred, because st/dri calls fence_finish with ctx = NULL, so the driver can't flush u_threaded_context. Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: Guard freedreno build with with_gallium_freedreno.Rob Clark2017-11-101-1/+3
| | | | | | | | | | This prevents build failures when libdrm_freedreno is unavailable, which started happening after the ir3_compiler build was enabled. (Patch by Rob, commit message by Ken). Fixes: fecd04a66ae ("freedreno/ir3: fix standalone compiler meson build") Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen10: Use the correct form of | for the RCPFE workaroundJason Ekstrand2017-11-101-2/+2
| | | | | | | | Found by inspection Fixes: d3d0fe4572f62474b86ef3a68405046c68b54062 Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make L3 configuration atom listen for TCS/TES program updates.Kenneth Graunke2017-11-101-0/+2
| | | | | | | | | | The L3 configuration code already considers the TCS and TES programs, but failed to listen for TCS/TES program changes. This was somehow missing. Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in get_pipeline_state_l3_weights.") Reviewed-by: Francisco Jerez <[email protected]>
* meson: build gallium-xlib based glxDylan Baker2017-11-104-2/+131
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: add support for xlib glxDylan Baker2017-11-102-5/+42
| | | | | | | | | | There is a bunch of churn in the main meson.build so that we can correctly set the auto tristate of GLX. In particular, don't build xlib-based glx when dri and gallium are disabled but vulkan is enabled, in that case just turn glx off. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: move gl pkgconfig generation out of glxDylan Baker2017-11-102-11/+14
| | | | | | | | | | | Because the same generation logic is required by xlib glx and gallium-xlib glx, it makes sense to pull it out. v2: - Ensure that libgl is defined before trying to generate a pkgconfig file with it. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: move wayland-egl into egl folderDylan Baker2017-11-102-3/+4
| | | | | | | | This ensure that it's properly guarded, but also makes the code clearer by grouping related things together. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: add nir_builder_opcodes_h to gallium_auxiliaryDylan Baker2017-11-101-1/+1
| | | | | | | | | This creates a dependency on this header being generated before trying to compile any of these targets, as well as passing the correct -I to the compiler to ensure it's included correctly. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/xlib: remove GL_{MAJOR,MINOR,TINY}Dylan Baker2017-11-101-5/+1
| | | | | | | | | | | | | These variables were removed from autotools in 2008 (sha: 80f68e1b6a0e5bd2da799c), but they have lived on here. The Scons build meanwhile doesn't set a patch/tiny version at all, just major and minor. This patch removes the unused variables and simply sets the version, leaving patch/tiny as 0 since that's what the autotools build as been doing forever. This shouldn't change any behavior. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi: get llvm types from acTimothy Arceri2017-11-111-4/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* glx/windows: Fix building libwindowsdri when libX11 headers are installed in ↵Jon Turney2017-11-101-0/+3
| | | | | | | a non-standard location Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
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