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* radv: add radv_meta_save() helperSamuel Pitoiset2017-10-069-73/+58
| | | | | | | | And merge radv_meta_save_novertex() with radv_meta_save_graphics_reset_vport_scissor_novertex(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: merge radv_meta_{save,restore}_pass() with RADV_META_SAVE_PASSSamuel Pitoiset2017-10-064-39/+22
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: convert all GFX operations to the RADV_META_SAVE_XXX flagsSamuel Pitoiset2017-10-067-13/+46
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: introduce the concept of meta save flagsSamuel Pitoiset2017-10-069-52/+85
| | | | | | | | | | | This will allow us to save/restore the different states on-demand based on the meta operation. For now, this saves/restores all states. Compute will follow once the graphics part is done. The main idea is to merge all save/restore helpers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused RADV_META_VERTEX_BINDING_COUNTSamuel Pitoiset2017-10-061-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: select the pipeline outside of the loop when decompressing htileSamuel Pitoiset2017-10-061-12/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_htile_enabled() helperSamuel Pitoiset2017-10-062-3/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: pass wanted format to intel_miptree_create_for_dri_imageTapani Pälli2017-10-065-40/+7
| | | | | | | | | | | | | | | | | Change b3a44ae7a4 caused regressions on Android where DRI and renderbuffer can disagree on the format being used. This patch removes the colorspace parameter and instead we pass renderbuffer format. For non-winsys images we still do srgb/linear modification in same manner as change b3a44ae7a4 wanted but take format from renderbuffer instead of DRI image. This patch fixes regressions seen with following test sets: dEQP-EGL.functional.color_clears* dEQP-EGL.functional.render* Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102999 Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival EvolvedMarek Olšák2017-10-066-0/+32
| | | | | | | | v2: use DB_META | PS_PARTIAL_FLUSH Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955 Reviewed-by: Samuel Pitoiset <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: inline struct si_sampler_viewsMarek Olšák2017-10-065-42/+37
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename si_textures_info -> si_samplers, si_images_info -> si_imagesMarek Olšák2017-10-063-20/+20
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fold needs_*_decompress_mask update into si_set_sampler_viewMarek Olšák2017-10-061-54/+46
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: simplify a loop in si_update_fb_dirtiness_after_renderingMarek Olšák2017-10-061-15/+11
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: properly document a buffer.store LLVM workaroundMarek Olšák2017-10-062-6/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use f32_0 and f32_1Marek Olšák2017-10-064-26/+26
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fold *gallivmMarek Olšák2017-10-062-52/+31
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: lp_type::length is always 1Marek Olšák2017-10-061-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use bld.elem_typeMarek Olšák2017-10-061-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use lp_build_const_*Marek Olšák2017-10-062-9/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ctx->ac.context and ctx->typesMarek Olšák2017-10-064-46/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ctx->ac.builderMarek Olšák2017-10-064-422/+342
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ctx->i/f32 types moreMarek Olšák2017-10-061-6/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use i32_0 and i32_1 moreMarek Olšák2017-10-062-11/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use bitcast in a few placesMarek Olšák2017-10-061-5/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac helpers for bitcastsMarek Olšák2017-10-064-128/+87
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
* glsl_to_tgsi: skip UARL for 1D registers if the driver doesn't need itMarek Olšák2017-10-062-9/+44
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl_to_tgsi: handle reladdr as TEMP in rename_temp_registers and dead_codeMarek Olšák2017-10-061-16/+44
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl_to_tgsi: each reladdr object should have only one parentMarek Olšák2017-10-062-5/+65
| | | | | | required by rename_temp_registers. Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl_to_tgsi: fix instruction order for bindless texturesMarek Olšák2017-10-061-4/+14
| | | | | | | | | We emitted instructions loading the bindless handle after the memory instruction. Cc: 17.2 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl_to_tgsi: enable copy propagation for tessellation shadersMarek Olšák2017-10-061-4/+3
| | | | | | just don't propagate output reads Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-062-5/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use si_get_indirect_index for TEMP indexingMarek Olšák2017-10-061-18/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use si_get_indirect_index for CONST indexingMarek Olšák2017-10-063-14/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/ureg: allow any register file in address operandsMarek Olšák2017-10-061-6/+0
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_TGSI_ANY_REG_AS_ADDRESSMarek Olšák2017-10-0617-0/+18
| | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: scan address operands (v2)Marek Olšák2017-10-061-1/+42
| | | | | | v2: set swizzled usage mask Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: set correct usage mask for tex offsets in scan_src_operandMarek Olšák2017-10-061-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: take advantage of already swizzled usage mask in scan_src_operandMarek Olšák2017-10-061-30/+17
| | | | | | It has always been a usage mask *after* swizzling. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi/scan: set non-valid src_index for tex offsets in scan_src_operandMarek Olšák2017-10-061-1/+1
| | | | | | tex offsets are not "Src" operands. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: implement tgsi_util_get_inst_usage_mask properlyMarek Olšák2017-10-063-124/+206
| | | | | | All opcodes are handled. Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: add docs for some existing pack opcodesMarek Olšák2017-10-061-3/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Enable VK_KHR_maintenance2 extension.Bas Nieuwenhuizen2017-10-062-0/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Make tess winding order a bit more intuitive.Bas Nieuwenhuizen2017-10-061-3/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Allow setting the domain origin in tess.Bas Nieuwenhuizen2017-10-061-1/+9
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Disable usage checks in metadata for images with extended usage data.Bas Nieuwenhuizen2017-10-061-1/+3
| | | | | | | The app can extend the usage, so knowing that the usage is limitied does not help us here. Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement querying the point clipping behavior.Bas Nieuwenhuizen2017-10-061-0/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* broadcom: Fix out-of-tree build include pathDaniel Stone2017-10-052-1/+5
| | | | | Reviewed-by: Eric Anholt <[email protected]> Fixes: 5b102160ae ("broadcom/genxml: Introduce a V3D packet/struct decoder.")
* meson: generate builddir/src/amd/vulkan/dev_icd.jsonBas Nieuwenhuizen2017-10-053-2/+9
| | | | Reviewed-by: Dylan Baker <[email protected]>
* mesa: Use a 565 format for GL_RGB and GL_UNSIGNED_SHORT_5_6_5 textures.Kenneth Graunke2017-10-051-0/+3
| | | | | | | | | | Found while trying to optimize an application. Not observed to help performance on i965, but should at least reduce the memory usage of such textures a bit. Reviewed-by: Eric Anholt <[email protected]> Tested-by: Eero Tamminen <[email protected]>
* intel/compiler: Don't propagate cmod into integer multipliesJason Ekstrand2017-10-052-0/+34
| | | | | | | No shader-db change on Sky Lake. Reviewed-by: Matt Turner <[email protected]> Cc: [email protected]
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 18:30:53 +0000