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* ilo: rename ilo_3d_pipeline*.[ch] to ilo_render*.[ch]Chia-I Wu2014-09-268-24/+24
| | | | | | They are used to build render engine commands, which can be more than 3D. Signed-off-by: Chia-I Wu <[email protected]>
* ilo: rename ilo_3d.[ch] to ilo_draw.[ch]Chia-I Wu2014-09-266-9/+9
| | | | | | | There is not much left in struct ilo_3d. We want to kill it and ilo_3d.[ch] will be bad names. Signed-off-by: Chia-I Wu <[email protected]>
* st/mesa: Use PIPE_USAGE_STAGING for GL_STATIC/DYNAMIC/STREAM_READ buffersMichel Dänzer2014-09-261-3/+5
| | | | | | | | | Such buffers can only be useful by reading from them with the CPU, so we need to make sure CPU reads are fast. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84178 Reviewed-by: Marek Olšák <[email protected]> Cc: [email protected]
* glsl: remove unused link_assign_uniform_block_offsetsTapani Pälli2014-09-262-37/+0
| | | | | | | ubo offsets are assigned by link_uniform_blocks since 514f8c7e Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Structures must have same name to be considered same type.Kalyan Kondapally2014-09-262-0/+22
| | | | | | | | | | | | | | | | | | | According to GLSL(4.2) and GLSL-ES (1.0, 3.0) spec, Structures must have the same name to be considered same type. We currently ignore the name check while checking if two records are same. This patch fixes this. Patch fixes failing tests in WebGL conformance test 'shaders-with-uniform-structs' when running Chrome on OpenGL ES. v2: Do not force name comparison with unnamed types (Tapani) v3: Cleanups (Matt) Signed-off-by: Kalyan Kondapally <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83934
* glsl: fix uniform location count used for glsl typesTapani Pälli2014-09-262-9/+12
| | | | | | | | | Patch fixes the slot count used by vector types and adds 1 slot to be used by image and sampler types. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82921
* gm107/ir: take relative pfetch offset into accountIlia Mirkin2014-09-261-1/+4
| | | | | | | | | There is no dedicated instruction for this, so just combine it with the constant offset. Acked-by: Ben Skeggs <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3" <[email protected]>
* gallivm: More fallout from disabling with LLVM 3.6Michel Dänzer2014-09-268-15/+26
| | | | | | | | The draw module would still try to use gallivm, causing many piglit tests to fail with an assertion failure. llvmpipe might have been similarly affected. Reviewed-by: Tom Stellard <[email protected]>
* gm107/ir: add support for indirect const buffer selectionIlia Mirkin2014-09-251-0/+14
| | | | | | | | This was missed in the commit that enabled it for fermi/kepler as part of ARB_gpu_shader5 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3" <[email protected]>
* gm107/ir: fix texture argument orderIlia Mirkin2014-09-252-5/+34
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3" <[email protected]>
* gm107/ir: fix manual TXD for array targetsIlia Mirkin2014-09-251-2/+3
| | | | | | | This parallels the fixes in commit afea9bae. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3" <[email protected]>
* nouveau: fix glCompressedTexImageIlia Mirkin2014-09-251-13/+52
| | | | | | | | mesa_texstore expects pixel data, not compressed data. For compressed textures, we want to just copy the bits in without any conversion. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* nv50/ir: avoid deleting pseudo instructions too earlyIlia Mirkin2014-09-251-1/+10
| | | | | | | | | | | What happens is that a SPLIT operation is part of the spill node, and as a pseudo op, the instruction gets erased after processing its first def. However the later defs still need to refer to it, so instead delay deleting until after that whole RA node is done processing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79462 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.2 10.3" <[email protected]>
* mesa/st: NumLayers is only valid for array texturesIlia Mirkin2014-09-253-3/+5
| | | | | | | | | | | For 3d textures, NumLayers is set to 1, which is not what we want. This fixes the newly added gl-layer-render-storage test (which constructs immutable 3d textures). Fixes regression introduced in d82bd7eb060. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84145 Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Michel Dänzer <[email protected]> Acked-by: Chris Forbes <[email protected]>
* nv50/ir: add some comments on edge classificationIlia Mirkin2014-09-251-0/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: fix 3d blit logic for odd depth/stencil formatsIlia Mirkin2014-09-252-7/+18
| | | | | Reported-by: David Heidelberger <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: add missing depth/stencil formats to tile flag selectionIlia Mirkin2014-09-252-0/+8
| | | | | Reported-by: David Heidelberger <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* vc4: Switch from errx() to fprintf() and abort().Eric Anholt2014-09-252-8/+15
| | | | | | | | These are pretty catastrophic, "should never happen" failure paths (though 4 tests in piglit hit them currently, due to a single bug). An abort() that you can gdb on easily is probably more useful than a clean exit, particularly since a bug in piglit framework right now is causing early exit(1)s to simply not be recorded in the results at all.
* vc4: Fix miplevel validation for raster textures.Eric Anholt2014-09-251-1/+1
| | | | | We were using the un-minified value, meaning we'd reject correctly laid out textures.
* mesa: Replace IS_NEGATIVE(x) with x < 0.0f.Matt Turner2014-09-255-21/+10
| | | | | | | | I only made IS_NEGATIVE(x) use signbit in commit 0f3ba405 in an attempt to fix 54805, but it didn't help. We didn't use signbit on some platforms and instead defined it to x < 0.0f. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Use PRINTLIKE macro.Matt Turner2014-09-251-8/+1
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* ralloc: Mark ralloc functions with gcc's malloc attribute.Matt Turner2014-09-252-8/+14
| | | | | | | Cuts a few hundred bytes from the DRI drivers, so it must give gcc some extra information. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Replace a priori knowledge of gcc attributes with configure tests.Matt Turner2014-09-252-10/+7
| | | | | | | | Note that I had to add support for testing the packed attribute to m4/ax_gcc_func_attribute.m4. Reviewed-by: Jason Ekstrand <[email protected]> [C bits] Reviewed-by: Ian Romanick <[email protected]>
* mesa: Replace a priori knowledge of gcc builtins with configure tests.Matt Turner2014-09-254-33/+30
| | | | | | | | | | | | | | Presumbly this will let clang and other compilers use the built-ins as well. Notice two changes specifically: - in _mesa_next_pow_two_64(), always use __builtin_clzll and add a static assertion that this is safe. - in macros.h, remove the clang-specific definition since it should be able to detect __builtin_unreachable in configure. Reviewed-by: Jason Ekstrand <[email protected]> [C bits] Reviewed-by: Ian Romanick <[email protected]>
* i965/compaction: Document instruction compaction capabilities.Matt Turner2014-09-251-0/+35
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Emit ELSE/ENDIF JIP with type D on Gen 7.Matt Turner2014-09-251-2/+2
| | | | | | | | | | The spec says the type must be W (JIP is 16-bits after all), but we've been emitting it with a UD type all along and have experienced no adverse effects. Changing the type to D allows ELSE and ENDIF instructions to be compacted. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Support compaction of control flow instructions.Matt Turner2014-09-251-14/+16
| | | | | | | | | | | | We're currently emitting compactable control flow instruction the wrong types, preventing their compaction. The next patch will fix this and actually enable compaction. On chips that cannot compact control flow instructions, attempts to find a match in the datatype table will fail. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Add support for G45.Matt Turner2014-09-251-15/+24
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add BRW_OPCODE_NENOP for G45.Matt Turner2014-09-252-2/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Add support for Gen5.Matt Turner2014-09-251-5/+210
| | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Ian Romanick <[email protected]>
* i965/compaction: Reduce size of compacted_counts[] array.Matt Turner2014-09-251-22/+37
| | | | | | | | | The array was previously indexed in units of brw_compact_inst (8-bytes), but before compaction all instructions are uncompacted, so every odd element was unused. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Use sizeof brw_inst/brw_compact_inst.Matt Turner2014-09-251-15/+17
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Increment offset in for loop.Matt Turner2014-09-251-3/+2
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/compaction: Make src_offset local to the for loop.Matt Turner2014-09-251-8/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Remove unnecessary is-compacted? check.Matt Turner2014-09-251-2/+3
| | | | | | | | Used to pass over previously compacted instructions in this loop, but no longer. No point in checking. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Don't set UIP on ELSE on Gen < 8.Matt Turner2014-09-251-1/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/compaction: Rework 3-src compaction logic.Matt Turner2014-09-251-5/+9
| | | | | | | | | It may be possible to create a contrived example in which a 3-src instruction would have been compacted on Gen < 8. I'd rather not discover it in the wild. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/sf: Disable instruction compaction.Matt Turner2014-09-251-1/+4
| | | | | | | | Currently a no-op, since instruction compaction isn't implemented for the generations that have a programmable strips-and-fans unit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Set JumpCount, not JIP, on ENDIF on Gen 6.Matt Turner2014-09-251-4/+7
| | | | | | | | Despite what the Sandybridge PRM says, ENDIF has Jump Count in <dst>, not JIP in <src1>. (The same mistake appears about WHILE as well). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Use VertexArray, not _VertexArray, in array size expressions.Kenneth Graunke2014-09-243-6/+6
| | | | | | | | | Both sizes are VERT_ATTRIB_MAX, so this has no effect. But it drops a few trivial uses of the derived state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Set correct array element in vbo_exec_vtx_init.Kenneth Graunke2014-09-241-1/+1
| | | | | | | | | | | I'm not familiar with this code, but this sure appears to be a typo. It looks like the intent is to set each array element, not arrays[0] each time. Notably, the loop just below uses "array", not "arrays". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: [email protected]
* mesa: Use proper structure for glGet*(GL_TEXTURE_COORD_ARRAY*).Kenneth Graunke2014-09-241-4/+4
| | | | | | | | | | | | | | | | | | The code in get.c that handles this uses ctx->Array.VAO->VertexAttrib, which is a gl_vertex_attrib_array structure, not a gl_client_array. The offsets of all fields happened to be the same in both structures, at least on x86_64. "Size," "Type," and "Stride" are obviously the same: both structures start with the same fields, in the same order. "Enabled" is dicier: there are different fields before it in both structures, including pointer sized values which might need special alignment. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: [email protected]
* mesa: Remove some dead helper functions.Kenneth Graunke2014-09-241-26/+0
| | | | | | | | | Dead since the _MaxElement removal, but these functions seemed generally applicable, so I decided to remove them in a separate patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* vc4: Compute max_index instead of trusting the rest of userspace.Eric Anholt2014-09-241-5/+13
| | | | | | | | | | | | | | max_index was coming from either the user telling us as part of glDrawRangeElements, or from an incidental calculation as part of some sort of primitive conversion fallback. Sometimes, it was just set to the default "I don't know" ~0 value. If it wasn't set to the actual max index, then the kernel would reject the draw call for allowing out-of-bounds VBO reads. So, compute the max index from the sizes of the VBOs, which isn't too expensive (unlike mapping and reading the index buffer) and is reliable. Fixes piglit vao-element-array-buffer.
* vc4: Move shader record setup before the draw call.Eric Anholt2014-09-241-38/+38
| | | | | The flush only happens after both are written, so we can do them in either order. This will let me compute max_index during the shader record setup.
* i965/vec4: Call calculate_cfg() in test programs to avoid crashing.Matt Turner2014-09-242-0/+2
| | | | Reported-by: Mark Janes <[email protected]>
* vc4: Add support for gl_PointCoord.Eric Anholt2014-09-241-0/+34
| | | | Fixes piglit glsl-fs-pointcoord, point-sprite, and fbo-gl_pointcoord.
* vc4: Add support for point size setting.Eric Anholt2014-09-246-6/+47
| | | | This is the support for both the global and per-vertex modes.
* vc4: Add support for line width setting.Eric Anholt2014-09-242-0/+5
| | | | | I don't see piglit tests for it, but this should be better than not emitting it at all.
* vc4: Actually add support for polygon offset.Eric Anholt2014-09-243-1/+28
| | | | | Setting the bit without setting the offset values is kind of useless. Fixes piglit polygon-offset (but not polygon-mode-offset).
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