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* radeonsi: increase coords array size for radeon_llvm_emit_prepare_cube_coordsMarek Olšák2015-03-182-2/+2
| | | | | | | | | radeon_llvm_emit_prepare_cube_coords uses coords[4] in some cases (TXB2 etc.) Discovered by Coverity. Reported by Ilia Mirkin. Cc: 10.5 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965: Defer the throttle until we submit new commandsChris Wilson2015-03-182-34/+44
| | | | | | | | | | | | | | | | | | | | | | Currently, we throttle before the user begins preparing commands for the next frame when we acquire the draw/read buffers. However, construction of the command buffer can itself take significant time relative to the frame time. If we move the throttle from the buffer acquire to the command submit phase we can allow the user to improve concurrency between the CPU and GPU (i.e. reduce the amount of time we waste inside the throttle). v2: Whitespace + delay throttling until after the next submission for greater parallelism Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]> [v1]
* i965: Throttle to the previous frameChris Wilson2015-03-183-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | In order to facilitate the concurrency offered by triple buffering and to offset the latency induced by swapping via an external process, which may incur extra rendering itself, only throttle to the previous frame and not the last. The second issue that mostly affects swap benchmarks, but also can incur jitter in the throttling, is that the throttle bo is closer to the next SwapBuffers rather than immediately after the previous SwapBuffers. Throttling to the previous frame doubles the maximum possible latency at the benefit of improving throughput and reducing jitter. v2: Rename "first_post_swapbuffer" batches array to a plain throttle_batch[] as the pluralisation was contorting the name and not making it clear as to whether it was the first batch or first_post_swap batch. Not least of which was that not all throttle points are SwapBuffers. Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Throttle rendering to an fboChris Wilson2015-03-183-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When rendering to an fbo, even though it may be acting as a winsys frontbuffer or just generally, we never throttle. However, when rendering to an fbo, there is no natural frame boundary. Conventionally we use SwapBuffers and glFinish, but potential callers avoid often glFinish for being too heavy handed (waiting on all outstanding rendering to complete). The kernel provides a soft-throttling option for this case that waits for rendering older than 20ms to be complete (that's a little too lax to be used for swapbuffers, but is here a useful safety net). The remaining choice is then either never to throttle, throttle after every draw call, or at after intermediate user defined point such as glFlush and thus all the implied flushes. This patch opts for the latter as that is the current method used for flushing to front buffers. v2: Defer the throttling from inside the flush to the next intel_prepare_render() and switch non-fbo frontbuffer throttling over to use the same lax method. The issuing being that glFlush()/intel_prepare_read() is just as likely to be called inside a tight loop and not at "frame" boundaries. v3: Rename from need_front_throttle to need_flush_throttle to avoid any ambiguity between front buffer rendering and fbo rendering. (Chad) v4: Whitespace Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* nir/peephole_select: Allow uniform/input loads and load_constJason Ekstrand2015-03-171-0/+25
| | | | | | | | | | | | | | | | | | | Shader-db results on HSW: total instructions in shared programs: 4174156 -> 4157291 (-0.40%) instructions in affected programs: 145397 -> 128532 (-11.60%) helped: 383 HURT: 0 GAINED: 20 LOST: 22 There are two more tests lost than gained. However, comparing this with GLSL IR vs. NIR results, the overall delta is reduced from 85/44 gained/lost on current master to 71/32 with this commit. Therefore, I think it's probably a boon since we are getting "closer" to where we were before. Reviewed-by: Connor Abbott <[email protected]>
* nir/peephole_select: Copy instructions into the block before the ifJason Ekstrand2015-03-171-13/+20
| | | | | | | | | Previously we tried to do poor-man's copy propagation as we created the select instructions. Instead, this commit just moves the instructions from the blocks inside the if into the block before. Copy propagation will take care of making sure we don't have any extra mov's in there for us. Reviewed-by: Connor Abbott <[email protected]>
* nir/peephole_select: Rename are_all_move_to_phi and use a switchJason Ekstrand2015-03-171-25/+31
| | | | Reviewed-by: Connor Abbott <[email protected]>
* glx: Handle out-of-sequence swap completion events correctly. (v2)Mario Kleiner2015-03-171-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for emitting INTEL_swap_events swap completion events needs to translate from 32-Bit sbc on the wire to 64-Bit sbc for the events and handle wraparound accordingly. It assumed that events would be sent by the server in the order their corresponding swap requests were emitted from the client, iow. sbc count should be always increasing. This was correct for DRI2. This is not always the case under the DRI3/Present backend, where the Present extension can execute presents and send out completion events in a different order than the submission order of the present requests, due to client code specifying targetMSC target vblank counts which are not strictly monotonically increasing. This confused the wraparound handling. This patch fixes the problem by handling 32-Bit wraparound in both directions. As long as successive swap completion events real 64-Bit sbc's don't differ by more than 2^30, this should be able to do the right thing. How this is supposed to work: awire->sbc contains the low 32-Bits of the true 64-Bit sbc of the current swap event, transmitted over the wire. glxDraw->lastEventSbc contains the low 32-Bits of the 64-Bit sbc of the most recently processed swap event. glxDraw->eventSbcWrap is a 64-Bit offset which tracks the upper 32-Bits of the current sbc. The final 64-Bit output sbc aevent->sbc is computed from the sum of awire->sbc and glxDraw->eventSbcWrap. Under DRI3/Present, swap completion events can be received slightly out of order due to non-monotic targetMsc specified by client code, e.g., present request submission: Submission sbc: 1 2 3 targetMsc: 10 11 9 Reception of completion events: Completion sbc: 3 1 2 The completion sequence 3, 1, 2 would confuse the old wraparound handling made for DRI2 as 1 < 3 --> Assumes a 32-Bit wraparound has happened when it hasn't. The client can queue multiple present requests, in the case of Mesa up to n requests for n-buffered rendering, e.g., n = 2-4 in the current Mesa GLX DRI3/Present implementation. In the case of direct Pixmap presents via xcb_present_pixmap() the number n is limited by the amount of memory available. We reasonably assume that the number of outstanding requests n is much less than 2 billion due to memory contraints and common sense. Therefore while the order of received sbc's can be a bit scrambled, successive 64-Bit sbc's won't deviate by much, a given sbc may be a few counts lower or higher than the previous received sbc. Therefore any large difference between the incoming awire->sbc and the last recorded glxDraw->lastEventSbc will be due to 32-Bit wraparound and we need to adapt glxDraw->eventSbcWrap accordingly to adjust the upper 32-Bits of the sbc. Two cases, correponding to the two if-statements in the patch: a) Previous sbc event was below the last 2^32 boundary, in the previous glxDraw->eventSbcWrap epoch, the new sbc event is in the next 2^32 epoch, therefore the low 32-Bit awire->sbc wrapped around to zero, or close to zero --> awire->sbc is apparently much lower than the glxDraw->lastEventSbc recorded for the previous epoch --> We need to increment glxDraw->eventSbcWrap by 2^32 to adjust the current epoch to be one higher than the previous one. --> Case a) also handles the old DRI2 behaviour. b) Previous sbc event was above closest 2^32 boundary, but now a late event from the previous 2^32 epoch arrives, with a true sbc that belongs to the previous 2^32 segment, so the awire->sbc of this late event has a high count close to 2^32, whereas glxDraw->lastEventSbc is closer to zero --> awire->sbc is much greater than glXDraw->lastEventSbc. --> We need to decrement glxDraw->eventSbcWrap by 2^32 to adjust the current epoch back to the previous lower epoch of this late completion event. We assume such a wraparound to a higher (a) epoch or lower (b) epoch has happened if awire->sbc and glxDraw->lastEventSbc differ by more than 2^30 counts, as such a difference can only happen on wraparound, or if somehow 2^30 present requests would be pending for a given drawable inside the server, which is rather unlikely. v2: Explain the reason for this patch and the new wraparound handling much more extensive in commit message, no code change wrt. initial version. Cc: "10.3 10.4 10.5" <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: constify r600_shader_tgsi_instruction lists.Emil Velikov2015-03-171-5/+5
| | | | | | | Massive list of constant data. Annotate it as such. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: kill off r600_shader_tgsi_instruction::{tgsi_opcode,is_op3}Emil Velikov2015-03-171-591/+589
| | | | | | | | Both of which are no longer used. Use designated initializer to make things obvious as people add/remove TGSI_OPCODEs. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: use the tgsi opcode from parse.FullToken.FullInstructionEmil Velikov2015-03-171-5/+8
| | | | | | | | | ... rather than the local one in inst_info->tgsi_opcode. This will allow us to simplify struct r600_shader_tgsi_instruction. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Apply gl_FrontFacing ? -1 : 1 optimization only for floatsIan Romanick2015-03-171-0/+3
| | | | | | | | | | | | | | | | At the very least, unreal4/sun-temple/102.shader_test uses this pattern for a signed integer result. However, that shader did not hit the optimization in the first place because it uses !gl_FrontFacing. I changed the shader to use remove the logical-not and reverse the other operands. I verified that incorrect code is generated before this change and correct code is generated after. Fixes fs-frontfacing-ternary-1-neg-1.shader_test. No shader-db changes. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Change try_opt_frontfacing_ternary to eliminate assertsIan Romanick2015-03-171-5/+2
| | | | | | | | If we check for the case that is actually necessary, the asserts become superfluous. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Handle CMP.nz ... 0 and AND.nz ... 1 similarly in cmod propagationIan Romanick2015-03-172-1/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Espically on platforms that do not natively generate 0u and ~0u for Boolean results, we generate a lot of sequences where a CMP is followed by an AND with 1. emit_bool_to_cond_code does this, for example. On ILK, this results in a sequence like: add(8) g3<1>F g8<8,8,1>F -g4<0,1,0>F cmp.l.f0(8) g3<1>D g3<8,8,1>F 0F and.nz.f0(8) null g3<8,8,1>D 1D (+f0) iff(8) Jump: 6 The AND.nz is obviously redundant. By propagating the cmod, we can instead generate add.l.f0(8) null g8<8,8,1>F -g4<0,1,0>F (+f0) iff(8) Jump: 6 Existing code already handles the propagation from the CMP to the ADD. Shader-db results: GM45 (0x2A42): total instructions in shared programs: 3550829 -> 3550788 (-0.00%) instructions in affected programs: 10028 -> 9987 (-0.41%) helped: 24 Iron Lake (0x0046): total instructions in shared programs: 4993146 -> 4993105 (-0.00%) instructions in affected programs: 9675 -> 9634 (-0.42%) helped: 24 Ivy Bridge (0x0166): total instructions in shared programs: 6291870 -> 6291794 (-0.00%) instructions in affected programs: 17914 -> 17838 (-0.42%) helped: 48 Haswell (0x0426): total instructions in shared programs: 5779256 -> 5779180 (-0.00%) instructions in affected programs: 16694 -> 16618 (-0.46%) helped: 48 Broadwell (0x162E): total instructions in shared programs: 6823088 -> 6823014 (-0.00%) instructions in affected programs: 15824 -> 15750 (-0.47%) helped: 46 No chage on Sandy Bridge or on any platform when NIR is used. v2: Add unit tests suggested by Matt. Remove spurious writes_flag() check on scan_inst when scan_inst is known to be BRW_OPCODE_CMP (also suggested by Matt). v3: Fix some comments and remove some explicit int() casts in fs_reg constructors in the unit tests. Both suggested by Matt. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Mark paths in linear <-> tiled functions as unreachable().Matt Turner2015-03-171-0/+16
| | | | | | | | | text data bss dec hex filename 9663 0 0 9663 25bf intel_tiled_memcpy.o before 8215 0 0 8215 2017 intel_tiled_memcpy.o after Reviewed-by: Carl Worth <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* egl: Remove eglQueryString virtual dispatch.Matt Turner2015-03-176-109/+12
| | | | Reviewed-by: Chad Versace <[email protected]>
* main: Correct _mesa_error with no format in bufferobj.c.Laura Ekstrand2015-03-171-1/+1
| | | | | | | This fixes Bug 89616, a build failure due to line 1639 of bufferobj.c: _mesa_error(ctx, GL_INVALID_OPERATION, func); Trivial.
* main: Cosmetic changes to GetBufferSubData.Laura Ekstrand2015-03-172-3/+3
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry point for GetNamedBufferSubData.Laura Ekstrand2015-03-174-0/+34
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* main: Cosmetic updates to GetBufferPointerv.Laura Ekstrand2015-03-171-4/+5
| | | | | | | v3: Review from Fredrik Hoglund -Split cosmetic refactor of GetBufferPointerv out into a separate commit Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry point for GetNamedBufferPointerv.Laura Ekstrand2015-03-174-0/+31
| | | | | | | v3: Review from Fredrik Hoglund -Split cosmetic refactor of GetBufferPointerv out into a separate commit Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry points for GetNamedBufferParameteri[64]v.Laura Ekstrand2015-03-174-0/+60
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* main: Refactor GetBufferParameteri[64]v.Laura Ekstrand2015-03-171-74/+45
| | | | | | v2: Split into a refactor commit and an entry point commit. Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry point for FlushMappedNamedBufferRange.Laura Ekstrand2015-03-174-0/+27
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* main: Refactor FlushMappedBufferRange.Laura Ekstrand2015-03-172-26/+40
| | | | | | | v2:-Remove "_mesa" from in front of static software fallback. -Split out the refactor from the addition of the DSA entry points. Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry point for UnmapNamedBuffer.Laura Ekstrand2015-03-174-13/+47
| | | | | | | | v2: review from Ian Romanick - Restore VBO_DEBUG and BOUNDS_CHECK - Remove _mesa from static software fallback unmap_buffer. Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry points for MapNamedBuffer[Range].Laura Ekstrand2015-03-174-3/+69
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* main: Refactor MapBuffer[Range].Laura Ekstrand2015-03-172-161/+133
| | | | | | | | | | v2: review from Jason Ekstrand - Split refactor from addition of DSA entry points. review from Ian Romanick - Remove "_mesa" from static software fallback map_buffer_range - Restore VBO_DEBUG and BOUNDS_CHECK Reviewed-by: Fredrik Höglund <[email protected]>
* main: Minor whitespace fixes in ClearNamedBuffer[Sub]Data.Laura Ekstrand2015-03-172-4/+4
| | | | Reviewed-by: Fredrik Höglund <[email protected]>
* main: Add entry points for ClearNamedBuffer[Sub]Data.Laura Ekstrand2015-03-174-0/+66
| | | | Reviewed-by: Martin Peres <[email protected]>
* main: Refactor ClearBuffer[Sub]Data.Laura Ekstrand2015-03-173-79/+69
| | | | | | | | v2: review by Jason Ekstrand - Split refactor of clear buffer sub data from addition of DSA entry points. Reviewed-by: Martin Peres <[email protected]>
* main: Add entry point for CopyNamedBufferSubData.Laura Ekstrand2015-03-174-33/+87
| | | | | | v2: remove _mesa in front of static software fallback. Reviewed-by: Martin Peres <[email protected]>
* main: Improve errors and style in BufferSubData.Laura Ekstrand2015-03-172-5/+9
| | | | | | | - More explicit error reporting. - Removed legacy style. Reviewed-by: Martin Peres <[email protected]>
* main: Add entry point for NamedBufferSubData.Laura Ekstrand2015-03-174-49/+97
| | | | | | | | | v2: review by Ian Romanick - Remove "_mesa" from name of static software fallback buffer_sub_data. - Remove mappedRange from _mesa_buffer_sub_data. - Removed some cosmetic changes to a separate commit. Reviewed-by: Martin Peres <[email protected]>
* main: Add entry point for NamedBufferData.Laura Ekstrand2015-03-174-22/+68
| | | | | | | | | | v2: review from Ian Romanick - Fix space in ARB_direct_state_access.xml. - Remove "_mesa" from the name of buffer_data static fallback. - Restore VBO_DEBUG and BOUNDS_CHECK. - Fix beginning of comment to start on same line as /* Reviewed-by: Martin Peres <[email protected]>
* main: Add entry point for NamedBufferStorage.Laura Ekstrand2015-03-174-17/+65
| | | | Reviewed-by: Martin Peres <[email protected]>
* main: Add entry point for CreateBuffers.Laura Ekstrand2015-03-174-14/+64
| | | | Reviewed-by: Martin Peres <[email protected]>
* Revert "main: _mesa_cube_level_complete checks NumLayers."Laura Ekstrand2015-03-171-4/+0
| | | | | | | | | | | | | | | | | This reverts commit 1ee000a0b6737d6c140d4f07b6044908b8ebfdc7. Failures with the GLES3 conformance suite and Synmark2 OGLHdrBloom revealed that this commit was in error. Extensive testing with Piglit prior to patch review and upstreaming did not reveal this problem because, in the few Piglit tests that test for cube completeness, NumLayers = 6. This is because all of the existing tests use TextureStorage to initialize the texture, which sets NumLayers. A new Piglit test has been sent to the mailing list that reproduces the bug related to this patch ("texturing: Testing glGenerateMipmap(GL_TEXTURE_CUBE_MAP) without glTexStorage2D"). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/skl: Send a message header when doing constant loads SIMD4x2Neil Roberts2015-03-173-6/+53
| | | | | | | | | | | | | | Commit 0ac4c272755c7 made it add a header for the send message when using SIMD4x2 on Skylake because without this it will end up using SIMD8D. However the patch missed the case when a sampler is being used to implement constant loads from a buffer surface in a SIMD4x2 vertex shader. This fixes 29 Piglit tests, mostly related to the ARL instruction in vertex programs. Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Anuj Phogat <[email protected]>
* i965/fs: in MAD optimizations, switch last argument to be immediateTapani Pälli2015-03-171-1/+10
| | | | | | | | | | | | | | | | | Commit bb33a31 introduced optimizations that transform cases of MAD in to simpler forms but it did not take in to account that src[0] can not be immediate and did not report progress. Patch switches src[0] and src[1] if src[0] is immediate and adds progress reporting. If both sources are immediates, this is taken care of by the same opt_algebraic pass on later run. v2: Fix for all cases, use temporary fs_reg (Matt, Kenneth) Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89569 Reviewed-by: Francisco Jerez <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]> Cc: "10.5" <[email protected]>
* gallivm: abort properly when running out of buffer space in lp_disassemblyRoland Scheidegger2015-03-171-4/+8
| | | | | | | Before this actually ran into an infinite loop printing out "invalid"... Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/dri: remove unused include from the automake/scons buildEmil Velikov2015-03-162-2/+0
| | | | | | | st/dri/common hasn't been around for a while. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* auxiliary/os: fix the android build - s/drm_munmap/os_munmap/Emil Velikov2015-03-161-2/+2
| | | | | | | | | Squash this silly typo introduced with commit c63eb5dd5ec(auxiliary/os: get the mmap/munmap wrappers working with android) Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/sw/kms: trivial cleanupsEmil Velikov2015-03-161-4/+2
| | | | | | | | Remove the forward declaration and make use of the DEBUG_PRINT macro for debug builds. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* loader: include <sys/stat.h> for non-sysfs buildsEmil Velikov2015-03-161-1/+1
| | | | | | | | | | | Required by fstat(), otherwise we'll error out due to implicit function declaration. Cc: "10.4 10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89530 Signed-off-by: Emil Velikov <[email protected]> Reported-by: Vadim Rutkovsky <[email protected]> Tested-by: Vadim Rutkovsky <[email protected]>
* radeonsi: implement TGSI_OPCODE_BFI (v2)Marek Olšák2015-03-161-0/+34
| | | | | | | v2: Don't use the intrinsics, the shader backend can recognize these patterns and generates optimal code automatically. Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: add a helper for extracting bitfields from parameters (v2)Marek Olšák2015-03-161-16/+27
| | | | | | | | This will be used a lot (especially by tessellation). v2: don't use the bfe intrinsic Reviewed-by: Tom Stellard <[email protected]>
* i965: Emit IF/ELSE/ENDIF/WHILE JIP with type W on Gen7Antia Puentes2015-03-161-4/+4
| | | | | | | | | | IvyBridge and Haswell PRM say that the JIP should be emitted with type W but we were using UD. The previous implementation did not show adverse effects, but IMHO it is safer to follow the specification thoroughly. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Antia Puentes <[email protected]>
* radeonsi: move scratch reloc state setupMarek Olšák2015-03-162-15/+22
| | | | | | | | - move it to its own function - do it after all states are emitted - bump SI_MAX_DRAW_CS_DWORDS Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: don't emit PA_SC_LINE_STIPPLE if not rendering linesMarek Olšák2015-03-161-0/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
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