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* ac/nir: remove unused nir_to_llvm_context:{defs,phis}Samuel Pitoiset2018-02-121-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* egl/gbm: Fix compiler warning about visual matching.Eric Anholt2018-02-121-1/+1
| | | | | | | The compiler doesn't know that num_visuals > 0. Fixes: 37a8d907cc16 ("egl/gbm: Ensure EGLConfigs match GBM surface format") Reviewed-by: Daniel Stone <[email protected]>
* freedreno: small fix for flushing dependent batchesRob Clark2018-02-101-0/+13
| | | | | | | | | | | | | | | Flush a resource's previous write_batch synchronously. Because a resource's associated batches are not updated until after the flush thread submits rendering to the kernel, this was causing a bit of confusion in the following loop. This fixes a bug that appeared with recent stk. Perhaps we need to re-work things a bit to clear out dependent patches in the ctx's thread and use a fence to deal with the period between when a flush is queued and when it is submitted to the kernel. But this will do until time permits a larger refactor. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: intra-block schedulingRob Clark2018-02-101-22/+104
| | | | | | | | | | | | Because of loops, we can't schedule all of a block's predecessors first. Instead just assume that the result consumed in a block was written far enough away in all paths into a block. And do an intra-block scheduling pass to figure out if there are any cases where we need to insert extra nop's. This works out better than always assuming the worst case (ie. that a value live into a block was written in the last instruction in the predecessor block). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: "boost" the depth of if/else conditionRob Clark2018-02-101-5/+6
| | | | | | | Account for the move to predicate register, to try to avoid needing to insert extra NOPs later. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: account for arrays in delayslot calcRob Clark2018-02-101-2/+30
| | | | | | | | | | | | | Normally false-deps are not something to consider, since they mostly exist for delay-slot related reasons: * barriers * ordering writes after read * SSBO/image access ordering The exception is a false-dependency on an array store. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more clever legalize algorithmRob Clark2018-02-101-42/+96
| | | | | | | | | | | | | | Previously we didn't handle flow control in legalize, and instead just set (ss)(sy) on the first instruction in every block. Which isn't very clever. Instead, consider output state of all predecessor blocks, so we only set a sync bit if needed for any possible path leading into a block. Because of loops, we can't require that all successor blocks are legalized before a given block, so instead run in a loop until results converge. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: track block predecessorsRob Clark2018-02-102-7/+25
| | | | | | Useful in the following patches. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: clean up dangling false-dep'sRob Clark2018-02-102-0/+46
| | | | | | | | | | | | | Maybe there is a better way for this.. where it comes useful is "array" loads, which end up as a false-dep for a later array store. If all the uses of an array load are CP'd into their consumer, it still leaves the dangling array load, leading to funny things like: mov.u32u32 r5.y, r0.y mov.u32u32 r5.y, r0.z Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle IMMED for mad 2nd src special caseRob Clark2018-02-101-2/+4
| | | | | | | Consider also immediates for swapping the first two srcs, because they can be lowered to constant. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove ir3 phi instructionRob Clark2018-02-108-205/+16
| | | | | | Now that we convert phi webs to ssa, we can drop all this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove lower_if_else passRob Clark2018-02-104-328/+0
| | | | | | Now that it is unused. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add experimental GCM passRob Clark2018-02-101-0/+7
| | | | | | | | | | Generally seems to do worse on instruction count and register usage, according to shader-db. But shader-db also doesn't do a very good job of weighting loop bodies, so that might not be totally valid. So add an env variable to enable GCM pass for easier experimentation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: change opt passesRob Clark2018-02-101-0/+14
| | | | | | | There are more useful nir passes added since initial conversion to nir. But ir3 was never updated to use them. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use peephole select passRob Clark2018-02-101-1/+1
| | | | | | | | | | | | | | | Agressively lowering all if/else to selects in some extreme cases results in much higher register pressure. Using peephole select instead with a modest threshold speeds up alu2 4x! 16 seems like a good limit, low enough to help alu2 but not too low that it penalizes everything else. With a bit better scheduling of the instruction that moves a value into a predicate register, we might be able to lower this limit a bit more in the future, but since we need 6 cycles from the move to predicate register to predicated branch, that puts some sort of lower bound on how far we can lower this threshold. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower phi webs to regsRob Clark2018-02-101-2/+1
| | | | | | | | | | nir's from_ssa pass is much better at avoiding inserting extra moves than our logic is. And lowering phi webs to regs just treats anything involved in a phi web as an array of length=1. Which with previous array related fixes in RA/etc ends up working out quite well. This cuts down on extra instructions and also helps with register pressure. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: separate arrays from groupsRob Clark2018-02-101-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make block/instruction serialno per-shaderRob Clark2018-02-102-4/+6
| | | | | | | Makes it easier to compare values seen in-game (where there are many shaders) to cmdline standalone compiler. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add spirv support to cmdline compilerRob Clark2018-02-101-3/+60
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't lower fsatRob Clark2018-02-103-1/+23
| | | | | | | | Instead, if possible fold (sat) flag into src, otherwise use: (sat)max.f rD, rS, rS Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add encoding/decoding for (sat) bitRob Clark2018-02-104-12/+42
| | | | | | | | Seems to be there since a3xx, but we always lowered fsat. But we can shave some instructions, especially in shaders that use lots of clamp(foo, 0.0, 1.0) by not lowering fsat. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: extend liverange of arraysRob Clark2018-02-101-0/+11
| | | | | | | Use livein state of other blocks to extend liverange of arrays when they are still needed by successor blocks. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: avoid extra mov's for "arrays"Rob Clark2018-02-101-3/+23
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: a couple more array fixesRob Clark2018-02-101-2/+15
| | | | | | (Plus a couple TODOs) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: keep array storesRob Clark2018-02-101-0/+6
| | | | | | | Since these are not in SSA form, add to block's keeps so it doesn't appear unused. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: propagate barrier informationRob Clark2018-02-101-0/+5
| | | | | | | | When eliminating movs, the instruction that is now directly using the src of the mov has the same scheduling order constraints as the original mov instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove pointless statementRob Clark2018-02-101-3/+0
| | | | | | Function ends after this if/else ladder, so it was pointless. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: some more debug printsRob Clark2018-02-102-0/+36
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix printing of relative branch offsetsRob Clark2018-02-102-3/+3
| | | | | | | | | | | | The number of bits depends on generation. But printing negative values with a5xx encoding (largest size) but compiling for a3xx or a4xx, would result in negative values printed as large positive values. I guess in practice huge negative branch offsets aren't likely (and if that is the case, the shader is probably too big to grok by reading the assembly). So just print using smallest bitfield size. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: be more clever with if/else jumpsRob Clark2018-02-101-1/+16
| | | | | | | | | | | Try to clean up things like: br !p0.x #2 br p0.x #something to eliminate the first branch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: avoid some spurious sync bitsRob Clark2018-02-101-1/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: print # of sync bits for shaderdbRob Clark2018-02-103-2/+18
| | | | | | When trying to optimize to reduce stalls, it is nice to see this info. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug trace for flushRob Clark2018-02-101-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* intel/compiler: fix 64bit value prints on 32bitGrazvydas Ignotas2018-02-102-3/+3
| | | | | | | | Fix the following: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t {aka long long unsigned int}. Reviewed-by: Lionel Landwerlin <[email protected]>
* st/glsl_to_nir: remove unused options variableTimothy Arceri2018-02-101-2/+0
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* st/radeonsi: enable disk cache for nirTimothy Arceri2018-02-102-8/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st: add nir shader disk cache supportTimothy Arceri2018-02-104-44/+135
| | | | | | v2: include compute shader support Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: move nir detection earlierTimothy Arceri2018-02-101-8/+7
| | | | | | | | | | | We move the nir check before the shader cache call so that we can call a nir based caching function in a following patch. Also with this change we simply check if vertex shaders support NIR rather than looping over the stages as mixing of shader types is not supported anyway. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: stop returning PIPE_SHADER_IR_NATIVE for PIPE_SHADER_CAP_PREFERRED_IRTimothy Arceri2018-02-101-3/+0
| | | | | | | | | Clover now checks PIPE_SHADER_CAP_SUPPORTED_IRS for native support instead. This change indirectly enables NIR support for compute shaders on radeonsi. Reviewed-by: Marek Olšák <[email protected]>
* r600: always return PIPE_SHADER_IR_TGSI for PIPE_SHADER_CAP_PREFERRED_IRTimothy Arceri2018-02-101-5/+1
| | | | | | | We now use PIPE_SHADER_CAP_SUPPORTED_IRS to check for native support in clover. Reviewed-by: Marek Olšák <[email protected]>
* clover: use PIPE_SHADER_CAP_SUPPORTED_IRS to discover IRTimothy Arceri2018-02-101-2/+9
| | | | | | | PIPE_SHADER_CAP_PREFERRED_IR was conflicting with PIPE_SHADER_IR_NIR for compute shaders, so we let clover pick the one it wants to use. Reviewed-by: Marek Olšák <[email protected]>
* r600: add PIPE_SHADER_IR_NATIVE to supported shaders for csTimothy Arceri2018-02-101-3/+7
| | | | | Acked-by: Pierre Moreau <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: add depth layout to scan passTimothy Arceri2018-02-101-0/+19
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi/nir: add FRAG_RESULT_COLOR to scan passTimothy Arceri2018-02-101-0/+6
| | | | | | Fixes a number of draw buffers piglit tests. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: convert nir_op_f2f32 src to a floatTimothy Arceri2018-02-101-0/+1
| | | | | | | | | | | | | | | | Fixes the following piglit test: ./bin/arb_vertex_attrib_64bit-check-explicit-location -auto -fbo Where we would end up with the nir such as: vec1 64 ssa_11 = pack_64_2x32_split ssa_9, ssa_10 vec1 32 ssa_12 = f2f32 ssa_2 And our pack_64_2x32_split nir to llvm code always produces a 64bit integer as output. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: fix some 64bit unpack assertsTimothy Arceri2018-02-101-2/+2
| | | | | | Previously the asserts did not take swizzles into account. Reviewed-by: Samuel Pitoiset <[email protected]>
* Revert "i965: prevent potentially null pointer access"Mark Janes2018-02-091-1/+1
| | | | | | | This reverts commit 712332ed54f14b5ee34c2990e351ca48992488b2, which caused over 90k failures in Mesa i965 CI. Reviewed-by: Dylan Baker <[email protected]>
* egl/gbm: Ensure EGLConfigs match GBM surface formatDaniel Stone2018-02-091-4/+48
| | | | | | | | | | | | | | | | | | | | | | | | When we create an EGL window surface on a GBM surface, ensure that the EGLConfig is compatible with the GBM format, notwithstanding XRGB/ARGB interchange. For example, rendering with an XRGB8888 EGLConfig on to an ARGB8888 gbm_surface (and vice-versa) are acceptable, but rendering with an XRGB2101010 EGLConfig on to an XRGB8888 gbm_surface will now be rejected. This was previously allowed through; when 10bpc formats were enabled, clients which picked a completely random EGL config and hoped/assumed they were XRGB8888 would break. If you have bisected a failure to start a GBM/KMS client to this commit, please look at its EGLConfig selection (e.g. through eglChooseConfigs), and add an EGL_NATIVE_VISUAL_ID == gbm_surface format match to the attribs for config selection. Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Tested-by: Ilia Mirkin <[email protected]>
* egl/gbm: Remove duplicate format tableDaniel Stone2018-02-091-18/+17
| | | | | | | | | | | | | | Now that we have mask/channel information in gbm_dri's format conversion table, we can remove the copy in EGL. As this table contains more formats (notably including R8 and RG8, which can be used for BO but not surface allocation), we now compare the masks of all channels when trying to find a suitable config. Without doing this, an XRGB8888 EGLConfig would match on an R8 format. Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Tested-by: Ilia Mirkin <[email protected]>
* gbm/dri: Expose visuals table through gbm_dri_deviceDaniel Stone2018-02-092-11/+19
| | | | | | Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Tested-by: Ilia Mirkin <[email protected]>
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