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* i965: Define the setup_vector_uniform_values() backend_visitor interface.Francisco Jerez2015-07-295-19/+44
| | | | | | | | | This cleans up the VEC4 implementation of setup_uniform_values() somewhat and will avoid duplication of the image uniform upload code by having a common interface to upload a vector of uniforms on either back-end. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove the emit_texture_gen*() fs_visitor methods.Francisco Jerez2015-07-292-629/+0
| | | | | | | This is now dead code. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Reimplement emit_mcs_fetch() in terms of logical sends.Francisco Jerez2015-07-292-24/+15
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Reimplement emit_texture() in terms of logical send messages.Francisco Jerez2015-07-291-17/+49
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Hook up SIMD lowering to handle texturing opcodes of unsupported width.Francisco Jerez2015-07-291-0/+33
| | | | | | | | | | | | | | | | | | This should match the set of cases in which we currently call fail() or no16() from the emit_texture_*() methods and the ones in which emit_texture_gen4() enables the SIMD16 workaround. Hint for reviewers: It's not a big deal if I happen to have missed some case here, it will just lead to an assertion failure down the road which is easily fixable, however being stricter than necessary won't cause any visible breakage, it would just decrease performance silently due to the unnecessary message splitting, so feel free to double-check that all cases listed here already cause a SIMD8/16 fall-back with the current texturing code -- You may want to skip over the Gen5-6 cases though if you don't have pencil and paper at hand. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement lowering of logical texturing opcodes on Gen4.Francisco Jerez2015-07-291-1/+107
| | | | | | | | | | | | | | | | | | | | | | | | Unlike its Gen5 and Gen7 counterparts this patch isn't a plain refactor of the previous Gen4 texturing code, it's more of a rewrite largely based on emit_texture_gen4_simd16(). The reason is that on the one hand the original emit_texture_gen4() code didn't seem easily fixable to be SIMD width-invariant and had plenty of clutter to support SIMD-width workarounds which are no longer required. On the other hand emit_texture_gen4_simd16() was missing a number of SIMD8-only opcodes. This should generalize both and roughly match their current behaviour where there is overlap. Incidentally this will fix the following piglits on Gen4: arb_shader_texture_lod.execution.arb_shader_texture_lod-texgrad arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 2d arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 3d arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d_projvec4 arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 3d Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement lowering of logical texturing opcodes on Gen5-6.Francisco Jerez2015-07-291-0/+103
| | | | | | | | | | This should be largely equivalent to emit_texture_gen5() except for slight codestyle changes and the use i965 opcodes instead of the ir_texture_opcode enum, see "i965/fs: Implement lowering of logical texturing opcodes on Gen7+." for the mapping between them. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Lower SHADER_OPCODE_TXF_UMS/MCS_LOGICAL too on Gen7+.Francisco Jerez2015-07-291-5/+11
| | | | | | | | These weren't being handled by emit_texture_gen7() but we can easily lower them here for consistency with other texturing opcodes. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement lowering of logical texturing opcodes on Gen7+.Francisco Jerez2015-07-291-1/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | This should be largely equivalent to emit_texture_gen7() except that we now get i965 sampling opcodes directly rather than ir_texture_opcode enum values. The mapping is as follows: - ir_tex -> SHADER_OPCODE_TEX - ir_txb -> FS_OPCODE_TXB - ir_txl -> SHADER_OPCODE_TXL - ir_txd -> SHADER_OPCODE_TXD - ir_txf -> SHADER_OPCODE_TXF - ir_txf_ms -> SHADER_OPCODE_TXF_CMS - ir_txs -> SHADER_OPCODE_TXS - ir_query_levels -> SHADER_OPCODE_TXS too, the visitor will make sure that the provided lod value is zero in this case. - ir_lod -> SHADER_OPCODE_LOD - ir_tg4 -> SHADER_OPCODE_TG4_OFFSET if the offset value is not immediate, SHADER_OPCODE_TG4 otherwise. Other than that there are only minor changes and style fixes like the implementation now being factored out in static functions to improve encapsulation. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix misleading comment regarding the message header in ↵Francisco Jerez2015-07-291-2/+3
| | | | | | | | | | emit_texture_gen7. This hasn't been overallocating space for the header for a long time. It still leaves the header uninitialized though until the generator fixes it. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Pass a BAD_FILE header source to LOAD_PAYLOAD in emit_texture_gen7().Francisco Jerez2015-07-291-1/+1
| | | | | | | | | So that it's left uninitialized by LOAD_PAYLOAD, we only need to reserve space for it in the message since it will be initialized implicitly by the generator. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix opt_zero_samples() for texturing ops not matching dispatch_width.Francisco Jerez2015-07-291-3/+3
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use exec_size instead of dispatch_width to determine the message ↵Francisco Jerez2015-07-291-4/+4
| | | | | | | | | | | | | variant. dispatch_width is global for a single compilation and doesn't necessarily match the desired execution width if we had to lower the original full-width instruction due to hardware limitations. These were all inside a Gen4-specific branch so this patch shouldn't have any effect on more recent hardware. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Define logical texture sampling opcodes.Francisco Jerez2015-07-293-0/+148
| | | | | | | | | | | | | | | | | Each logical variant is largely equivalent to the original opcode but instead of taking a single payload source it expects the arguments separately as individual sources, like: tex_logical dst, coordinates, shadow_c, lod, lod2, sample_index, mcs, sampler, offset, num_coordinate_components, num_grad_components This patch defines the opcodes and usual instruction boilerplate, including a placeholder lowering function provided mostly as documentation for their source registers. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Reimplement emit_single_fb_write() in terms of logical framebuffer ↵Francisco Jerez2015-07-292-187/+21
| | | | | | | | | | | | | writes. The only non-trivial thing it still has to do is figure out where to take the src/dst depth values from and predicate the instruction if discard is in use. The manual SIMD unrolling logic in the dual-source case goes away because this is now handled transparently by the SIMD lowering pass. Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement lowering of logical framebuffer writes.Francisco Jerez2015-07-291-1/+136
| | | | | | | | | | | | | | | | | | | | | This does essentially the same thing as fs_visitor::emit_single_fb_write(), with some slight differences: - We don't have to worry about exec_size and use_2nd_half anymore, 16-wide sources have already been lowered to 8-wide thanks to the previous commit and the manual argument unzipping is no longer required. - The src/dst_depth and sample_mask values are now explicit sources of the instruction instead of being taken from the visitor state directly. The same goes for the kill-pixel mask that will be passed to the instruction explicitly as predicate. - Everything is now done in static functions to improve encapsulation. Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Hook up SIMD lowering to unroll FB writes of unsupported width.Francisco Jerez2015-07-291-0/+9
| | | | | | | | This shouldn't have any effect because we don't emit logical framebuffer writes yet. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.Francisco Jerez2015-07-294-42/+0
| | | | | | | This is now unused. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Don't attempt to copy the useless half of oMask for SIMD8 FB writes.Francisco Jerez2015-07-291-8/+18
| | | | | | | | | | | | | | | | | | There's no need to initialize the wrong half of oMask in the payload when we're doing an 8-wide framebuffer write because it will be ignored by the hardware anyway. By doing it this way we can let the SIMD lowering pass split the sample_mask source as a regular per-channel source, otherwise we would have to introduce some sort of per-instruction source query or use fs_inst::header_size for the lowering pass to be able to find out whether some source is header-like, and leave the source untouched in that case. As a bonus this achieves the same purpose as the previous code without making use of the SET_OMASK pseudo-instruction, which will be removed in a future commit. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Move up Gen6 no16 check to emit_fb_writes().Francisco Jerez2015-07-291-9/+11
| | | | | | | And update the comment. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Move up prog_data->uses_omask assignment up to brw_codegen_wm_prog().Francisco Jerez2015-07-292-3/+2
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Simplify control flow in emit_single_fb_write().Francisco Jerez2015-07-291-12/+16
| | | | | | | | Flatten the if ladder to match the way that the ordering of these fields is specified in the hardware documentation a bit more closely. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix slight layering violation in emit_single_fb_writes().Francisco Jerez2015-07-291-12/+10
| | | | | | | | | | | | | | | | | In cases where the color0 argument wasn't being provided, emit_single_fb_writes() would take the alpha channel directly from the visitor state instead of taking it from its arguments. This sort of hack didn't fit nicely into the logical send-message approach because all parameters of the instruction have to be visible to the SIMD lowering pass for it to be able to split them into halves at all. Fix it by using LOAD_PAYLOAD in fs_visitor::emit_fb_writes() to provide an actual color0 vector with undefined contents except for the alpha component to match the previous behavior when no color buffers are enabled. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make sure that the type sizes are compatible during copy propagation.Francisco Jerez2015-07-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's surprising that we weren't checking for this already. A future patch will cause code like the following to be emitted: MOV(16) tmp<1>:uw, src MOV(8) dst<1>:ud, tmp<8,8,1>:ud The second MOV comes from the expansion of a LOAD_PAYLOAD header copy, so I don't have control over its types. Copy propagation will happily turn this into: MOV(8) dst<1>:ud, src Which has different semantics. Fix it by preventing propagation in cases where a single channel of the instruction would span several channels of the copy (this requirement could in fact be relaxed if the copy is just a trivial memcpy, but this case is unusual enough that I don't think it matters in practice). I'm deliberately only checking if the type of the instruction is larger than the original, because the converse case seems to be handled correctly already in the code below. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Honour the instruction force_sechalf and exec_size fields for FB ↵Francisco Jerez2015-07-291-2/+2
| | | | | | | | | | writes. We were previously guessing the half based on the EOT flag which seems rather gross. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Define logical framebuffer write opcode.Francisco Jerez2015-07-294-1/+53
| | | | | | | | | | | | | | | | The logical variant is largely equivalent to the original opcode but instead of taking a single payload source it expects its arguments that make up the payload separately as individual sources, like: fb_write_logical null, color0, color1, src0_alpha, src_depth, dst_depth, sample_mask, num_components This patch defines the opcode and usual instruction boilerplate, including a placeholder lowering function provided mainly as self-documentation. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement pass to lower instructions of unsupported SIMD width.Francisco Jerez2015-07-292-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This lowering pass implements an algorithm to expand SIMDN instructions into a sequence of SIMDM instructions in cases where the hardware doesn't support the original execution size natively for some particular instruction. The most important use-cases are: - Lowering send message instructions that don't support SIMD16 natively into SIMD8 (several texturing, framebuffer write and typed surface operations). - Lowering messages that don't support SIMD8 natively into SIMD16 (*cough*gen4*cough*). - 64-bit precision operations (e.g. FP64 and 64-bit integer multiplication). - SIMD32. The algorithm works by splitting the sources of the original instruction into chunks of width appropriate for the lowered instructions, and then interleaving the results component-wise into the destination of the original instruction. The pass is controlled by the get_lowered_simd_width() function that currently just returns the original execution size making the whole pass a no-op for the moment until some user is introduced. Reviewed-by: Jason Ekstrand <[email protected]> v2: Reverse order of the source transformations and split_inst emit call to make the code a bit easier to understand.
* i965/fs: Fix return value of fs_inst::regs_read() for BAD_FILE.Francisco Jerez2015-07-291-0/+1
| | | | | | | | | | | | Typically BAD_FILE sources are used to mark a source as not present what implies that no registers are read. This will become much more frequent with logical send opcodes which have a large number of sources, many of them optionally used and marked as BAD_FILE when they aren't applicable. It will prove to be useful to be able to rely on the value of regs_read() regardless of whether a source is present or not. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add builder emit method taking a variable number of source registers.Francisco Jerez2015-07-291-3/+12
| | | | | | | | And start using it in fs_builder::LOAD_PAYLOAD(). This will be used to emit logical send message opcodes which have an unusually large number of arguments. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add stub lowering pass for logical send-message opcodes.Francisco Jerez2015-07-292-1/+29
| | | | | | | | | | | | | | | | This pass will house ad-hoc lowering code for several send message-like virtual opcodes that will represent their logically independent arguments as separate instruction sources rather than as a single payload blob. This pass will basically just take the separate arguments that are supposed to be part of the payload and concatenate them to construct a message in the form required by the hardware. Virtual instructions in separate-source form will eventually allow some simplification of the visitor code and make several transformations easier like lowering SIMD16 instructions to SIMD8 algorithmically in cases where the hardware doesn't support the former natively. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Factor out source components calculation to a separate method.Francisco Jerez2015-07-292-10/+24
| | | | | | | | | | | | | | | | | | This cleans up fs_inst::regs_read() slightly by disentangling the calculation of "components" from the handling of message payload arguments. This will also simplify the SIMD lowering and logical send message lowering passes, because it will avoid expressions like 'regs_read * REG_SIZE / component_size' which are not only ugly, they may be inaccurate because regs_read rounds up the result to the closest register multiple so they could give incorrect results when the component size is lower than one register (e.g. uniforms). This didn't seem to be a problem right now because all such expressions happen to be dealing with per-channel GRFs only currently, but that's by no means obvious so better be safe than sorry. v2: Split PIXEL_X/Y and LINTERP into separate case blocks. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Simplify instruction rewrite loop in the register coalesce pass.Francisco Jerez2015-07-291-14/+13
| | | | | | | | | | | | For some reason the loop that rewrites all occurrences of the coalesced register was iterating over all possible offsets until it would find one that compares equal to the offset of a source or destination of any instruction in the program. Since the mapping between old and new offsets is already available in the regs_to_offset array and we know that the whole register has been coalesced we can just look it up. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Fix rewrite of the second half of 16-wide coalesced registers.Francisco Jerez2015-07-291-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | The register coalesce pass wasn't rewriting the destination and sources of instructions that accessed the second half of a coalesced register previously copied with a 16-wide MOV instruction. E.g.: | ADD (16) vgrf0:f, vgrf0:f, 1.0:f | MOV (16) vgrf1:f, vgrf0:f | MOV (8) vgrf2:f, vgrf0+1:f { sechalf } would get incorrectly register-coalesced into: | ADD (16) vgrf1:f, vgrf1:f, 1.0:f | MOV (8) vgrf2:f, vgrf0+1:f { sechalf } The reason is that the mov[i] pointer was being left equal to NULL for every other register. The fact that we've made it to the rewrite loop implies that the whole register will be coalesced, so it doesn't seem right not to update something that uses it depending on whether mov[i] is NULL or not. Fixes an amount of texturing and image_load_store piglit tests on my SIMD-lowering branch. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Detect multi-register MOVs correctly in register_coalesce.Francisco Jerez2015-07-291-1/+1
| | | | | | | | | | | register_coalesce() was considering the exec_size of the MOV instruction alone to decide whether the register at offset+1 of the source VGRF was being copied to inst->dst.reg_offset+1 of the destination VGRF, which is only a valid assumption if the move has a 32-bit execution type. Use regs_read() instead to find out the number of registers copied by the instruction. Reviewed-by: Jason Ekstrand <[email protected]>
* radeon: add support for streams to the common streamout code. (v2)Dave Airlie2015-07-296-15/+50
| | | | | | | | | | | | This adds to the common radeon streamout code, support for multiple streams. It updates radeonsi/r600 to set the enabled mask up. v2: update for changes in previous patch. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon: move streamout buffer config to streamout enable function. (v2)Dave Airlie2015-07-292-9/+15
| | | | | | | | | | This will be used here later. v2: update atom sizes add check for old vs new enabled mask Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/es3.1: enable GL_ARB_explicit_uniform_location for GLES 3.1Marta Lofstedt2015-07-292-1/+9
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa/es3.1: enable GL_ARB_compute_shader for GLES 3.1Marta Lofstedt2015-07-292-10/+16
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa/es3.1: enable GL_ARB_texture_gather for GLES 3.1Marta Lofstedt2015-07-292-2/+10
| | | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: enable GL_ARB_texture_multisample for GLES 3.1Marta Lofstedt2015-07-292-6/+14
| | | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: enable GL_ARB_shader_atomic_counters for GLES 3.1Marta Lofstedt2015-07-292-9/+17
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa/es3.1: enable GL_ARB_shader_image_load_store for GLES 3.1Marta Lofstedt2015-07-292-6/+17
| | | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa/es3.1: Add ES 3.1 handling to get.c and get_hash_generator.pyMarta Lofstedt2015-07-292-5/+12
| | | | | Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa: Return INVALID_ENUM in glClearBufferiv() when buffer is not color or ↵Eduardo Lima Mitev2015-07-291-0/+12
| | | | | | | | | | | | | | | stencil Page 497 of the PDF, section '17.4.3.1 Clearing Individual Buffers' of the OpenGL 4.5 spec states: "An INVALID_ENUM error is generated by ClearBufferiv and ClearNamedFramebufferiv if buffer is not COLOR or STENCIL." Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.buffer.clear_bufferiv Reviewed-by: Ian Romanick <[email protected]>
* i965: Use real stage in "Unsupported form of variable indexing" warning.Kenneth Graunke2015-07-281-2/+3
| | | | | | | Other stages can be miserably slow too! Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: Fix a bug where LHS swizzles of swizzles were too small.Kenneth Graunke2015-07-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple shader such as vec4 color; color.xy.x = 1.0; would cause ir_assignment::set_lhs() to generate bogus IR: (swiz xy (swiz x (constant float (1.0)))) We were setting the number of components of each new RHS swizzle based on the highest channel used in the LHS swizzle. So, .xy.y would generate (swiz xy (swiz xx ...)), while .xy.x would break. Our existing Piglit test happened to use .xzy.z, which worked, since 'z' is the third component, resulting in an xxx swizzle. This patch sets the number of swizzle components based on the size of the LHS swizzle's inner value, so we always have the correct number at each step. Fixes new Piglit tests glsl-vs-swizzle-swizzle-lhs-[23]. Fixes ir_validate assertions in in Metro 2033 Redux. v2: Move num_components updating completely out of update_rhs_swizzle (suggested by Timothy Arceri). Simplify. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: verify location when dual source blendingTapani Pälli2015-07-291-0/+19
| | | | | | | | | | | | Same check is made for glBindFragDataLocationIndexed but it was missing when using layout qualifiers. Fixes following Piglit test: arb_blend_func_extended-output-location Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: move max_index calc to assign_attribute_or_color_locationsTapani Pälli2015-07-291-8/+15
| | | | | | | | | | | Change function to get all gl_constants for inspection, this is used by follow-up patch. v2: rebase, update function documentation Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* vc4: Skip re-emitting the shader_rec if it's unchanged.Eric Anholt2015-07-285-43/+158
| | | | | | | | It's a bunch of work for us to emit it (and its uniforms), more work for the kernel to validate it, and additional work for the CLE to read it. Improves es2gears framerate by about 50%. Signed-off-by: Eric Anholt <[email protected]>
* vc4: Drop unused vpm_offset value.Eric Anholt2015-07-281-3/+0
| | | | | It's been dead since we started doing VS/CS attr offset setup during shader compile.
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