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* iris: fix SBA flushing by refactoring codeKenneth Graunke2019-02-211-50/+25
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* iris: do PIPELINE_SELECT for render engine, add flushes, GLK hacksKenneth Graunke2019-02-211-6/+80
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* iris: hack to avoid memorybarriers out the wazooKenneth Graunke2019-02-211-3/+7
| | | | | | | | we don't want to emit piles of pipe controls to a compute batch if it isn't necessary... prevents double-batch-wraps in cs-op-selection-bool-bvec4-bvec4 (but it's still kinda a big ol' hack...)
* iris: don't let render/compute contexts stomp each other's dirty bitsKenneth Graunke2019-02-212-3/+10
| | | | only clear what you process
* iris: better dirty checkingKenneth Graunke2019-02-212-52/+67
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* iris: rewrite grid surface handlingKenneth Graunke2019-02-213-57/+73
| | | | | | | now we only upload a new grid when it's actually changed, which saves us from having to emit a new binding table every time it changes. this also moves a bunch of non-gen-specific stuff out of iris_state.c
* iris: XXX for compute state tracking :/Kenneth Graunke2019-02-211-0/+1
| | | | | Maybe we should just move dirty to batch, it would help with the reset stuff too
* iris: fix whitespaceKenneth Graunke2019-02-211-3/+3
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* iris: bail if SLM is neededKenneth Graunke2019-02-211-0/+3
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* iris: leave XXX about unnecessary binding table uploadsKenneth Graunke2019-02-211-0/+2
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* iris: drop unnecessary #ifdefsKenneth Graunke2019-02-211-2/+0
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* iris: drop XXX that Jordan handledKenneth Graunke2019-02-211-2/+0
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* iris/compute: Support indirect compute dispatchJordan Justen2019-02-211-0/+21
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Push subgroup-idJordan Justen2019-02-213-6/+37
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Flush compute batch on memory-barriersJordan Justen2019-02-211-0/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Provide binding table entry for gl_NumWorkGroupsJordan Justen2019-02-211-6/+53
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Wait on compute batch when mappingJordan Justen2019-02-211-0/+5
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/program: Don't try to push ubo ranges for computeJordan Justen2019-02-211-1/+2
| | | | | | | | | | | | | | | | | | We only can push constants for compute shaders from one range. Gallium glsl-to-nir (src/mesa/state_tracker/st_glsl_to_nir.cpp) lowers all uniform accesses to a ubo. Unfortunately we also load the subgroup-id as a uniform in the compiler. Since we use the 1 push range for this subgroup-id, we then lose the ability to actually push the ubo with all the normal user uniform values. In other words, there is lots of room for performance improvement, but at least retrieving the uniforms as pull-constants is functional for now. Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Get group counts from grid->gridJordan Justen2019-02-211-3/+3
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Flush compute batchesJordan Justen2019-02-211-0/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Add MEDIA_STATE_FLUSH following WALKERJordan Justen2019-02-211-0/+2
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris: Add iris_restore_compute_saved_bosJordan Justen2019-02-211-5/+54
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris: Add IRIS_DIRTY_CONSTANTS_CSJordan Justen2019-02-211-14/+15
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris/compute: Set mask bits on PIPELINE_SELECTJordan Justen2019-02-211-0/+3
| | | | Signed-off-by: Jordan Justen <[email protected]>
* iris: little bits of compute basicsKenneth Graunke2019-02-219-7/+325
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* iris: drop XXX's about swizzlingKenneth Graunke2019-02-211-4/+4
| | | | pretty sure this is unnecessary on modern HW
* iris: drop dead format //'sKenneth Graunke2019-02-211-56/+0
| | | | these just aren't supported
* iris: yesKenneth Graunke2019-02-211-1/+0
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* iris: initial compute capsKenneth Graunke2019-02-211-3/+62
| | | | RET macro borrowed from freedreno
* iris: Enable fb fetchKenneth Graunke2019-02-211-0/+1
| | | | needed for ES 3.2
* iris: advertise GL_ARB_shader_texture_image_samplesKenneth Graunke2019-02-211-0/+1
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* iris: Set num_uniforms in bytesJordan Justen2019-02-211-0/+6
| | | | | | Ref: brw_nir_lower_uniforms, type_size_scalar_bytes Signed-off-by: Jordan Justen <[email protected]>
* iris: move images next to textures in binding tableKenneth Graunke2019-02-212-14/+12
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* iris: null for non-existent cbufsKenneth Graunke2019-02-213-26/+46
| | | | prevents BTs from being shifted down incorrectly
* iris: actually set image accessKenneth Graunke2019-02-211-0/+2
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* iris: Don't lower image formats for write-only imagesJason Ekstrand2019-02-211-1/+3
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* iris: set image access correctlyKenneth Graunke2019-02-212-12/+16
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* iris: bother with BTIsKenneth Graunke2019-02-212-4/+24
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* iris: implement set_shader_images hookKenneth Graunke2019-02-212-0/+91
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* iris: lower storage image derefsKenneth Graunke2019-02-211-0/+83
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* iris: set the binding table sizeKenneth Graunke2019-02-211-2/+2
| | | | | | we weren't doing mark_surface_used on images (i965 does it while uploading the unnecessary image uniforms), so our binding tables were too small...
* iris: X32_S8X24 :/Kenneth Graunke2019-02-211-5/+1
| | | | | | | | This can happen when faking Z32_S8X24 and setting StencilSampling = true I guess we'll just turn it into S8_UINT... Fixes KHR-GL45.texture_swizzle.functional
* iris: enable I/L formatsKenneth Graunke2019-02-211-81/+67
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* iris: Use R/RG instead of I/L/A when samplingKenneth Graunke2019-02-211-0/+31
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* iris: rework format translation apisKenneth Graunke2019-02-215-53/+81
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* iris: Allow PIPE_CONTROL with Stall at Scoreboard and RT flushKenneth Graunke2019-02-211-1/+5
| | | | It's nonsensical, but not illegal, and mandatory on Icelake
* iris: add gen11 to genX_callKenneth Graunke2019-02-211-0/+3
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* iris: inline stage_from_pipe to avoid unused warningsKenneth Graunke2019-02-211-1/+1
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* iris: pipe to scs -> iris_pipe.hKenneth Graunke2019-02-212-17/+17
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* iris: force persample interp capKenneth Graunke2019-02-211-0/+1
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