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* r600g/sb: fix issues cause by GLSL switching to loops for switchDave Airlie2014-12-021-12/+38
| | | | | | | | | | | | | | | | | | | Since 73dd50acf6d244979c2a657906aa56d3ac60d550 glsl: implement switch flow control using a loop The SB backend was falling over in an assert or crashing. Tracked this down to the loops having no repeats, but requiring a working break, initial code just called the loop handler for all non-if statements, but this caused a regression in tests/shaders/dead-code-break-interaction.shader_test. So I had to add further code to detect if all the departure nodes are empty and avoid generating an empty loop for that case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86089 Cc: "10.4" <[email protected]> Reviewed-By: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/a4xx: alpha blend fixesRob Clark2014-12-013-1/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix DRAW initiator encoding of index sizeRob Clark2014-12-011-8/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2014-12-015-23/+22
| | | | Signed-off-by: Rob Clark <[email protected]>
* i965/vec4: Rewrite dead code elimination to use live in/out.Matt Turner2014-12-013-155/+170
| | | | | | | | | | | | | | | Improves 359 shaders by >=10% 114 shaders by >=20% 91 shaders by >=30% 82 shaders by >=40% 22 shaders by >=50% 4 shaders by >=60% 2 shaders by >=80% total instructions in shared programs: 5845346 -> 5822422 (-0.39%) instructions in affected programs: 364979 -> 342055 (-6.28%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Track liveness of the flag register.Matt Turner2014-12-012-0/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove opt_drop_redundant_mov_to_flags().Matt Turner2014-12-012-32/+0
| | | | | | Dead code elimination now handles this. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use const fs_reg & rather than a copy or pointer.Matt Turner2014-12-014-18/+17
| | | | | | Also while we're touching var_from_reg, just make it an inline function. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Dead code eliminate instructions writing the flag.Matt Turner2014-12-011-4/+22
| | | | | | | | | Most prominently helps Natural Selection 2, which has a surprising number shaders that do very complicated things before drawing black. instructions in affected programs: 21052 -> 16978 (-19.35%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Track liveness of the flag register.Matt Turner2014-12-012-0/+41
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use local pointer to block_data in live intervals.Matt Turner2014-12-015-49/+61
| | | | | | | The next patch will be simplified because of this, and makes reading the code a lot easier. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Make live_intervals part of the vec4_visitor class.Matt Turner2014-12-013-11/+11
| | | | | | Like in fs_visitor. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Treat the FB_WRITE as predicated if we're discarding.Matt Turner2014-12-012-1/+5
| | | | | | | | Pre-Haswell hardware couldn't actually predicate it, but it's easier to pretend as if it's predicated in the visitor since it will generate a MOV from f0.1. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't treat IF or WHILE with cmod as writing the flag.Matt Turner2014-12-012-2/+6
| | | | | | | Sandybridge's IF and WHILE instructions can do an embedded comparison with conditional mod. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Disassemble tdr and tm registers properly.Matt Turner2014-12-011-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* main, glsl: Bump max known desktop glsl version to 4.50Jordan Justen2014-12-013-4/+14
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl/cs: Change gl_WorkGroupSize from ivec3 to uvec3Jordan Justen2014-12-011-4/+4
| | | | | | | | | | | As documented in: https://www.opengl.org/registry/specs/ARB/compute_shader.txt const uvec3 gl_WorkGroupSize; Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: avoid anonymous struct in float <-> VF conversionsJonathan Gray2014-12-011-8/+8
| | | | | | | | | | | Anonymous structures are only supported with newer versions of GCC. They will not work with GCC 4.2.1 used by OpenBSD or GCC 4.4.7 shipped with RHEL6 going by a commit to fix a similiar problem in radeonsi earlier in the year (74388dd24bc7fdb9e62ec18096163f5426e03fbf). Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Jonathan Gray <[email protected]>
* mesa: fix arithmetic error in _mesa_compute_compressed_pixelstore()Brian Paul2014-12-011-1/+1
| | | | | | | | We need parenthesis around the expression which computes the number of blocks per row. Reviewed-by: Matt Turner <[email protected]> Cc: "10.3 10.4" <[email protected]>
* vbo: also print buffer object pointer in vbo_print_vertex_list()Brian Paul2014-12-011-2/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: some improvements for print_list()Brian Paul2014-12-013-73/+88
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: inline/remove _mesa_polygon_stipple()Brian Paul2014-12-012-32/+10
| | | | | | Was not called from any other place. Reviewed-by: Kenneth Graunke <[email protected]>
* svga: fix comment typoBrian Paul2014-12-011-1/+1
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* mesa: remove unused functions in prog_execute.cBrian Paul2014-12-011-74/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add include path to fix building of pipe-loader codeBrian Paul2014-12-011-0/+1
| | | | | | The pipe-loader code wasn't finding util/u_atomic.h Reviewed-by: Matt Turner <[email protected]>
* graw: Avoid 'near'/'far' variables.José Fonseca2014-12-018-24/+24
| | | | | They are defined by windows.h, which got included slightly more frequently than before with u_atomic.h
* i965/fs: Clean up some whitespace in reg_allocate.Matt Turner2014-12-011-2/+2
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* ra: Don't use regs as the ralloc context.Matt Turner2014-12-011-1/+1
| | | | | | | | | | The i965 backends pass something out of 'screen', which is allocated per-process, making using this as a ralloc context not thread-safe. All callers ra_alloc_interference_graph() already ralloc_free() its return value. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Initialize INTEL_DEBUG once per process.Matt Turner2014-12-011-1/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Initialize compaction tables once per process.Matt Turner2014-12-011-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Initialize static temporaries_allocate_names once per process.Matt Turner2014-12-011-1/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* util/u_atomic: Fix the unlocked implementation.José Fonseca2014-12-011-6/+6
| | | | | | | | | | | | | | | | | | It was totally broken: - p_atomic_dec_zero() was returning the negation of the expected value - p_atomic_inc_return()/p_atomic_dec_return() was post-incrementing/decrementing, hence returning the old value instead of the new - p_atomic_cmpxchg() was returning the new value on success, instead of the old It is clear this never used in the past. I wonder if it wouldn't be better to yank it altogether. Reviewed-by: Matt Turner <[email protected]>
* util/u_atomic: Add a simple test.José Fonseca2014-12-012-0/+146
| | | | | | | | | | | | | It was much easier for me to verify things build and run as expected with this simple test, than building and testing whole Mesa. With scons the test can be build and run merely by doing: scons u_atomic_test Building the test with autotools is left as a future exercise. Reviewed-by: Matt Turner <[email protected]>
* util: Make u_atomic.h typeless.Matt Turner2014-12-011-113/+93
| | | | | | | | | | | | like how C11's stdatomic.h provides generic functions. GCC's __sync_* builtins already take a variety of types, so that's simple. MSVC and Sun Studio don't, but we can implement it with something that looks a little crazy but is actually quite readable. Thanks to Jose for some MSVC fixes! Reviewed-by: Jose Fonseca <[email protected]>
* util: Use stdbool.h's bool rather than "boolean".Matt Turner2014-12-011-3/+5
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* util: Remove u_atomic.h's GCC inline assembly.Matt Turner2014-12-011-122/+0
| | | | | | | GCC >= 4.1 support the __sync_* intrinsics. That seems like a sufficiently old baseline. Reviewed-by: Jose Fonseca <[email protected]>
* util: Remove u_atomic.h's MSVC inline assembly.Matt Turner2014-12-011-70/+0
| | | | | | | There was already an intrinsics path that implemented all of the same functions, plus more. Reviewed-by: Jose Fonseca <[email protected]>
* util: Remove u_atomic.h's Gallium dependence.Matt Turner2014-12-011-9/+6
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* util: s/INLINE/inline/ in u_atomic.h.Matt Turner2014-12-011-29/+29
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* util: Move u_atomic.h to src/util.Matt Turner2014-12-012-0/+2
| | | | | | To be shared outside of Gallium. Reviewed-by: Jose Fonseca <[email protected]>
* vc4: Introduce scheduling of QPU instructions.Eric Anholt2014-12-016-126/+722
| | | | | | | | | | | | This doesn't reschedule much currently, just tries to fit things into the regfile A/B write-versus-read slots (the cause of the improvements in shader-db), and hide texture fetch latency by scheduling setup early and results collection late (haven't performance tested it). This infrastructure will be important for doing instruction pairing, though. shader-db2 results: total instructions in shared programs: 61874 -> 59583 (-3.70%) instructions in affected programs: 50677 -> 48386 (-4.52%)
* vc4: Drop the explicit scoreboard wait.Eric Anholt2014-12-011-12/+11
| | | | This is actually implicitly handled by the TLB operations.
* vc4: Also deal with VPM reads at thread end.Eric Anholt2014-12-011-2/+6
| | | | | Prevents a regression with QPU scheduling, which happens to put the no-op reads for unused VPM contents end up at the end of the program.
* vc4: Fix assertion about SFU versus texturing.Eric Anholt2014-12-011-3/+4
| | | | | | | We're supposed to be checking that nothing else writes r4, which is done by the TMU result collection signal, not the coordinate setup. Avoids a regression when QPU instruction scheduling is introduced.
* vc4: Add another check for invalid TLB scoreboard handling.Eric Anholt2014-12-013-8/+39
| | | | This was caught by an assertion in the simulator.
* freedreno/a4xx: invalidate cache when vbo's changeRob Clark2014-12-011-0/+7
| | | | | | | | | Otherwise vertex shader can see stale cache data. This in particular happens when the same vbo is updated and reused. Not sure yet if vbo's at differing addresses but bound to same vertex buffer slot could have issues, but seems safest to flush whenever new vertex buffers are bound. Signed-off-by: Rob Clark <[email protected]>
* st/mesa: avoid exposing EXT_texture_integer for pre-GLSL 1.30Ilia Mirkin2014-11-301-0/+3
| | | | | | | | | For drivers building up to GL(ES)3, only expose the actual extension if the API will let it be used (e.g. via overrides/debug flags that enable higher versions). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a3xx: add missing integer formats and enable renderingIlia Mirkin2014-11-301-3/+30
| | | | | | | | The mesa state tracker doesn't fall back on similar integer formats, so they must all be provided. Remove the restriction against integer color rendering. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: enable sampling from integer texturesIlia Mirkin2014-11-305-5/+55
| | | | | | | | We need to produce a u32 destination type on integer sampling instructions, so keep that in a shader key set based on the currently-bound textures. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: allow each generation to hook into sampler view settingIlia Mirkin2014-11-305-3/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
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