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* i965/fs: allow unit tests to dump the final patched assemblyTopi Pohjolainen2014-01-232-8/+10
| | | | | | | | | | | | | | Unit tests comparing generated blorp programs to known good need to have the dump in designated file instead of in default standard output. The comparison also expects the jump counters of if-else-instructions to be correctly set and hence the dump needs to be taken _after_ 'patch_IF_ELSE()' is run (the default dump of the fs_generator does this before). v2 (Paul): dropped the redundant 'dump_enabled' argument Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap brw_IF/ELSE/ENDIF() into eu-emitterTopi Pohjolainen2014-01-232-9/+23
| | | | | | | v2 (Paul): renamed emit_if() to emit_cmp_if() Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap RNDD (/brw_RNDD(&func, /emit_rndd(/)Topi Pohjolainen2014-01-232-2/+8
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap FRC (/brw_FRC(&func, /emit_frc(/)Topi Pohjolainen2014-01-232-4/+10
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap MUL (/brw_MUL(&func, /emit_mul(/)Topi Pohjolainen2014-01-232-9/+16
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap OR (/brw_OR(&func, /emit_or(/)Topi Pohjolainen2014-01-232-24/+31
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap SHL (/brw_SHL(&func, /emit_shl(/)Topi Pohjolainen2014-01-232-12/+19
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap SHR (/brw_SHR(&func, /emit_shr(/)Topi Pohjolainen2014-01-232-12/+19
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap ADD (/brw_ADD(&func, /emit_add(/)Topi Pohjolainen2014-01-232-18/+32
| | | | | | | | In addition, the special case requiring explicit execution size control is wrapped manually. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap AND (/brw_AND(&func, /emit_and(/)Topi Pohjolainen2014-01-232-39/+46
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap MOV (/brw_MOV(&func, /emit_mov(/)Topi Pohjolainen2014-01-232-35/+45
| | | | | | | | In addition, the two special cases requiring explicit execution size control are wrapped manually. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap emission of if-equal-assignmentTopi Pohjolainen2014-01-232-24/+12
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap emission of conditional assignmentTopi Pohjolainen2014-01-232-15/+15
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of sample combining into eu-emitterTopi Pohjolainen2014-01-233-9/+24
| | | | | | | | | v2 (Paul): pass the combining opcode as an argument to emit_combine(). This keeps manual_blend_average() selfcontained documentation wise. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of rt-write into eu-emitterTopi Pohjolainen2014-01-233-10/+28
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of texture lookup into eu-emitterTopi Pohjolainen2014-01-233-22/+60
| | | | | | | | | | | Resolving of the hardware message type is moved into the emitter also in preparation for switching to use fs_generator. The generator wants to translate the high level op-code into the message type and hence the emitter needs to know the original op-code. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: introduce non-compressed equivalent of tex_cmsTopi Pohjolainen2014-01-234-0/+13
| | | | | | | v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: rename tex_ms to tex_cmsTopi Pohjolainen2014-01-2310-17/+17
| | | | | | | | | | Prepares for the introduction of non-compressed multi-sampled lookup used in the blorp programs. v2: now also taking into account gen8 Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of pixel kill into eu-emitterTopi Pohjolainen2014-01-233-25/+38
| | | | | | | | | The combination of four separate comparison operations and and the masked "and" require special treatment when moving to FS LIR. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: introduce separate eu-emitter for blit compilerTopi Pohjolainen2014-01-234-38/+113
| | | | | | | | | | | | Prepares for presenting blorp blit programs using FS IR that allows EU-assembly generation using i965 glsl-compiler backend (fs_generator). v2: rebased on top of endif-jump counter fix (moving the added brw_set_uip_jip() into the emitter) Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Support 32 texture image units on Haswell+.Kenneth Graunke2014-01-222-4/+7
| | | | | | | | | | | | | | | | | | | | The Intel closed source OpenGL driver recently began supporting 32 texture image units on Haswell. This makes the open source driver support 32 as well. Earlier generations don't have the message header field required to support more than 16 sampler states, so we continue to advertise 16 there. On Haswell, this causes us to advertise: - GL_MAX_TEXTURE_IMAGE_UNITS = 32 - GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32 - GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96 instead of the old values of 16, 16, and 48. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.Kenneth Graunke2014-01-221-1/+2
| | | | | | | | | | BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to support the new larger value. On older platforms, we don't want to allocate the extra space - it would just be a waste. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* mesa: Bump MAX_TEXTURE_IMAGE_UNITS to 32.Kenneth Graunke2014-01-221-1/+1
| | | | | | | | This allows drivers to optionally support more than 16 texture units. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Support arbitrarily large sampler state indices on Haswell+.Kenneth Graunke2014-01-222-3/+26
| | | | | | | | | | Like the scalar backend, we add an offset to the "Sampler State Pointer" field to select a group of 16 samplers, then use the "Sampler Index" field to select within that group. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Refactor sampler message setup.Kenneth Graunke2014-01-221-17/+22
| | | | | | | | | | The next patch adds an additional case where the message header is necessary. So we want to do the g0 copy if inst->header_present is set, rather than inst->texture_offset. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Don't set header_present if texel offsets are all 0.Kenneth Graunke2014-01-221-9/+8
| | | | | | | | | | | | | | In theory, a shader might use textureOffset() but set all the texel offsets to zero. In that case, we don't actually need to set up the message header - zero is the implicit default. By moving the texture_offset setup before the header_present setup, we can easily only set header_present when there are non-zero texel offset values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Support arbitrarily large sampler state indices on Haswell+.Kenneth Graunke2014-01-222-2/+22
| | | | | | | | | | | | | | | | | The message descriptor's "Sampler Index" field is only 4 bits (on all generations of hardware), so it can only represent indices 0 through 15. Haswell introduced a new field in the message header - "Sampler State Pointer". Normally, this is copied straight from g0, but we can also add a byte offset (as long as it's a multiple of 32). This patch uses a "Sampler State Pointer" offset to select a group of 16 sampler states, and then uses the "Sampler Index" field to select the state within that group. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Plumb sampler index into emit_texture_gen7.Kenneth Graunke2014-01-223-4/+4
| | | | | | | | We'll need this in the next patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Refactor sampler message header to duplicate less code.Kenneth Graunke2014-01-221-25/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Use get_element_ud to shorten texture header access.Kenneth Graunke2014-01-221-2/+1
| | | | | | | | This is shorter, easier to read, and further from the 80 column limit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* gallium/util: util_format_srgb should not return FORMAT_NONE for sRGB formatsMarek Olšák2014-01-231-0/+3
| | | | | | | | | This fixes a serious regression introduced in 4e549ddb500cf677b6fa16d9ebdfa67cc23da097. Cc: 9.2 10.0 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: remove PIPE_CAP_SCALED_RESOLVEMarek Olšák2014-01-2312-14/+0
| | | | | | | If any driver doesn't support this, it can use a blit after resolving the samples. Reviewed-by: Brian Paul <[email protected]>
* radeonsi: use hardware scissors correctlyMarek Olšák2014-01-231-35/+20
| | | | | | | | | | | | Use the WINDOW and VPORT scissors for the framebuffer and scissor test, respectively. The other two scissors are disabled (they cover the max fb size). We actually have 16 VPORT scissors, which will map well to ARB_viewport_array. Also, we don't need to write SC_WINDOW_OFFSET with this commit, because it's disabled everywhere. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: handle R600_CONTEXT_PS_PARTIAL_FLUSH in si_emit_cache_flushMarek Olšák2014-01-231-1/+2
| | | | | | For consistency only, This is unused by radeonsi currently. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: if discarding whole buffer range, discard whole resource insteadMarek Olšák2014-01-231-0/+8
| | | | | | | Also set the unsynchronized flag if the whole resource was discarded to avoid doing buffer-busy checks again. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/u_upload_mgr: don't expose u_upload_flushMarek Olšák2014-01-232-22/+4
| | | | | | | It's unused and shouldn't be used at all in my opinion. If some driver doesn't support the unsynchronized flag, u_upload_mgr should avoid the synchronization by other means, e.g. by using the DONTBLOCK flag.
* gallium/hud: just unmap the upload vertex buffer instead of recreating itMarek Olšák2014-01-231-1/+1
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* gallium/vl: use u_upload_mgr to upload vertices for vl_compositorMarek Olšák2014-01-232-32/+20
| | | | | | | This is the recommended way for streaming vertices. Always use this if you need to upload vertices every frame. Reviewed-by: Christian König <[email protected]>
* intel: Fix initial MakeCurrent for single-buffer drawablesKristian Høgsberg2014-01-221-6/+4
| | | | | | | | | | | | | | | Commit 05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 attempts to eliminate the call to intel_update_renderbuffer() in the case where we already have a drawbuffer for the drawable. Unfortunately this only checks the back left renderbuffer, which breaks in case of single buffer drawables. This means that the initial viewport will not be set in that case. Instead, we now check whether the initial viewport has not been set, in which case we call out to intel_update_renderbuffer(). https://bugs.freedesktop.org/show_bug.cgi?id=73862 Signed-off-by: Kristian Høgsberg <[email protected]>
* glsl: Simplify aggregate type inference to prepare for ARB_arrays_of_arrays.Paul Berry2014-01-225-148/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the time it is not necessary to perform type inference to compile GLSL; the type of every expression can be inferred from the contents of the expression itself (and previous type declarations). The exception is aggregate initializers: their type is determined by the LHS of the variable being assigned to. For example, in the statement: mat2 foo = { { 1, 2 }, { 3, 4 } }; the type of { 1, 2 } is only known to be vec2 (as opposed to, say, ivec2, uvec2, int[2], or a struct) because of the fact that the result is being assigned to a mat2. Previous to this patch, we handled this situation by doing some type inference during parsing: when parsing a declaration like the one above, we would call _mesa_set_aggregate_type(), which would infer the type of each aggregate initializer and store it in the corresponding ast_aggregate_initializer::constructor_type field. Since this happened at parse time, we couldn't do the type inference using glsl_type objects; we had to use ast_type_specifiers, which are much more awkward to work with. Things are about to get more complicated when we add support for ARB_arrays_of_arrays. This patch simplifies things by postponing the call to _mesa_set_aggregate_type() until ast-to-hir time, when we have access to glsl_type objects. As a side benefit, we only need to have one call to _mesa_set_aggregate_type() now, instead of six. Reviewed-by: Matt Turner <[email protected]>
* clover: Don't crash on NULL global buffer objects.Jan Vesely2014-01-221-11/+23
| | | | | | | | | | | | | | | | | | Specs say "If the argument is a buffer object, the arg_value pointer can be NULL or point to a NULL value in which case a NULL value will be used as the value for the argument declared as a pointer to __global or __constant memory in the kernel." So don't crash when somebody does that. v2: Insert NULL into input buffer instead of buffer handle pair Fix constant_argument too Drop r600 driver changes v3: Fix inserting NULL pointer Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* meta: Move loop variable declaration outside loop.Vinson Lee2014-01-211-1/+3
| | | | | | | | | | | | | | | | Fixes MSVC build error introduced with commit 69b258cb4636315b4c1aaaceeedd1eed8af98ba8. meta.c(618) : error C2143: syntax error : missing ';' before 'type' meta.c(618) : error C2143: syntax error : missing ')' before 'type' meta.c(618) : error C2065: 'i' : undeclared identifier meta.c(618) : warning C4552: '<' : operator has no effect; expected operator with side-effect meta.c(618) : error C2059: syntax error : ')' meta.c(618) : error C2143: syntax error : missing ';' before '{' meta.c(619) : error C2065: 'i' : undeclared identifier meta.c(620) : error C2065: 'i' : undeclared identifier Signed-off-by: Vinson Lee <[email protected]>
* i965/blorp: use BRW_COMPRESSION_2NDHALF for second half LPRTopi Pohjolainen2014-01-222-28/+42
| | | | | | | | | No known bugs fixed but this is now in line with fs-generator. No regresssions on IVB. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: patch jump counters also for endifTopi Pohjolainen2014-01-222-3/+5
| | | | | | | | | | | | | | | | | No known bugs fixed but this is now in line with fs-generator. No regresssions on IVB. Eric further explained that: "The endif jump, since it's forward, is just an optimization to have set right -- otherwise, the GPU will just step forward instruction by instruction until it hits something else that updates the per-channel PC." Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Change redundant code into loops in texstate.c.Paul Berry2014-01-211-46/+29
| | | | | | | This is possible now that ctx->Shader.CurrentProgram is an array. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Change redundant code into loops in shaderapi.c.Paul Berry2014-01-211-30/+9
| | | | | | | This is possible now that ctx->Shader.CurrentProgram is an array. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Remove ad-hoc arrays of gl_shader_program.Paul Berry2014-01-213-15/+3
| | | | | | | | Now that we have a ctx->Shader.CurrentProgram array, we can just use it directly. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* meta: Replace save_state::{Vertex,Geometry,Fragment}Shader with an array.Paul Berry2014-01-211-16/+14
| | | | | | | | Since ctx->Shader.Current{Vertex,Geometry,Fragment}Program is an array, this allows some meta code to be rolled up into loops. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Fix comments to refer to the new ctx->Shader.CurrentProgram array.Paul Berry2014-01-213-6/+6
| | | | | Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Fold long lines introduced by the previous patch.Paul Berry2014-01-218-17/+32
| | | | | Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
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