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* glsl: Remove textureGradOffset built-ins taking samplerCube parameters.Kenneth Graunke2011-11-103-9/+0
| | | | | | | | | These simply don't exist in the 1.30 specification---none of the Offset variants allow samplerCube. This must have been a cut and paste error from textureGrad, which /does/ allow cubemaps. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glsl: Fix misnamed textureProjOffset prototypes in built-in profiles.Kenneth Graunke2011-11-102-62/+62
| | | | | | | | Due to a cut and paste error, these were accidentally misnamed textureProj() rather than textureProjOffset(). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glsl: Remove texture built-ins with 'bias' from 1.30 VS profile.Kenneth Graunke2011-11-101-118/+4
| | | | | | | | | | | From the GLSL 1.30 spec, section 8.7 "Texture Lookup Functions": "In all functions below, the bias parameter is optional for fragment shaders. The bias parameter is not accepted in a vertex shader." This was a cut and paste mistake. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Put a proper sampler count in 3DSTATE_VS.Kenneth Graunke2011-11-102-3/+5
| | | | | | | See similar code for 3DSTATE_WM. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload SAMPLER_STATE pointers for the VS on Ivybridge.Kenneth Graunke2011-11-101-1/+7
| | | | | | | See similar code in gen7_wm_state.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move and rename "wm sampler" fields to just "sampler".Kenneth Graunke2011-11-109-33/+37
| | | | | | | | | | | | | brw_wm_samplers actually enables any active samplers regardless of what pipeline stage is using them, so it doesn't make much sense for it to be WM-specific. So, rename it to "brw_samplers." To properly generalize it, move sampler_count and sampler_offset from brw_context::wm to a new brw_context::sampler that can be shared without looking strange. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Clean up code for VS pull constant surface creation.Kenneth Graunke2011-11-103-64/+20
| | | | | | | | | | Like for the WM pull constants, we can merge the former prepare/emit stages into one tracked state atom. Furthermore, the code that used to handle the binding table was removed in the last commit, leaving some rather silly looking short functions that can easily be folded in. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use a single binding table for all pipeline stages.Kenneth Graunke2011-11-109-85/+80
| | | | | | | | | | | | | | | | | | | | | | | Although the hardware supports separate binding tables for each pipeline stage, we don't see much advantage over a single shared table. Consider the contents of the binding table: - Textures (16) - Draw buffers (8) - Pull constant buffers (1 for VS, 1 for WM) OpenGL's texture bindings are global: the same set of textures is available to all shader targets. So our binding table entries for textures would be exactly the same in every table. There are only two pull constant buffers (not many), and although draw buffers aren't interesting to the VS, it shouldn't hurt to have them in the table. The hardware supports up to 254 binding table entries, and we currently only use 26. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Split brw_wm_surfaces state into renderbuffer and texture atoms.Kenneth Graunke2011-11-103-15/+35
| | | | | | | | | | | | | First, the texturing setup code is relevant for all pipeline stages, while renderbuffer surfaces are only used by the WM. Secondly, renderbuffer and texture setup depends on a different set of dirty bits. There's no reason to walk the array of textures when changing draw buffers, or vice-versa. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Combine the two WM pull constant tracked state atoms.Kenneth Graunke2011-11-104-59/+16
| | | | | | | | | | | | | | | | These were only split for historical reasons: brw_wm_constants used to be the "prepare" step, while brw_wm_constant_surface was "emit". Now that both happen at emit time, it makes sense to combine them. Call the newly combined state atom "brw_wm_pull_constants" to indicate help distinguish it from the Gen6+ atoms that handle push constants. Finally, remove the BRW_NEW_WM_CONSTBUF dirty bit entirely now that it's never flagged nor used. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Rename gen6_*_constants tracked state atoms to "push_constants".Kenneth Graunke2011-11-104-8/+8
| | | | | | | | | | | | | | | When reading the "brw_wm_constants" and "gen6_wm_constants" atoms side-by-side, I initially failed to notice the crucial difference: the Gen6 atoms are for Push Constants, while brw_wm_constants handles Pull Constants. (Gen4/5 Push Constants are handled by "brw_curbe.") Renaming these should clarify the code and save me from constant confusion over the fact that "gen6_wm_constants" isn't just a newer version of "brw_wm_constants." Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove nr_surfaces computation from brw_update_wm_surfaces.Kenneth Graunke2011-11-101-11/+1
| | | | | | | | | | | | This code is fairly fragile, as it depends on the ordering of the entries in the binding table, which will change soon. Also, stop listening on the BRW_NEW_WM_CONSTBUF dirty bit as it's no longer required. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).Kenneth Graunke2011-11-1010-50/+6
| | | | | | | | | | | | | | | | | | | | | | These fields control how many entries the hardware prefetches into the state cache, so they only impact performance, not correctness. However, it's not clear how to use this in a way that's beneficial. According to the documentation, kernels "using a large number" of entries may wish to program this to zero to avoid thrashing the cache; it's unclear how many is too many. Also, Ironlake's WM was missing this feature entirely---the count had to be zero. The dirty bit tracking to handle this complicates the surface state and binding table setup; removing it should simplify things and make future refactoring easier. So just set 0 for the number of entries rather than trying to compute and track it. Appears to have no impact on Nexuiz and OpenArena on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove outdated comment about CACHE_NEW_SURF_BIND dirty bit.Kenneth Graunke2011-11-101-2/+1
| | | | | | | | | | The comment states that brw_update_vs_constant_surface produces a CACHE_NEW_SURF_BIND dirty bit, but it doesn't. In fact, that bit no longer even exists. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove BRW_NEW_NR_VS_SURFACES dirty bit from brw_vs_surfaces.Kenneth Graunke2011-11-101-1/+0
| | | | | | | | | | | | | | | brw_vs_surfaces _produces_ the BRW_NEW_NR_VS_SURFACES dirty bit, so it makes no sense for it to subscribe to it. Fixes an assertion failure in many piglit tests when INTEL_DEBUG is set: brw_state_upload.c:484: void brw_upload_state(struct brw_context *): Assertion `!check_state(&examined, &generated)' failed. One such piglit test is vs-uniform-array-mat2-col-rd.shader_test. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add missing CACHE_NEW_WM_PROG dirty bit to WM pull constants.Kenneth Graunke2011-11-101-2/+3
| | | | | | | | | | | | | Comparing brw_upload_vs_pull_constants and brw_upload_wm_pull_constants, it became evident that something was amiss: the VS code had both CACHE_NEW_VS_PROG and BRW_NEW_VERTEX_PROGRAM, while the WM code was missing the CACHE_NEW_WM_PROG flag. Not observed to fix anything, but likely necessary. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Use new vtable entries for surface state updating functions.Kenneth Graunke2011-11-104-126/+13
| | | | | | | | | | Now that we have vtable entries in place, we should use them. This allows us to drop the cut and pasted Gen7 brw_tracked_state atoms as they now do exactly the same thing as their brw_wm_surface_state counterparts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add new vtable entries for surface state updating functions.Kenneth Graunke2011-11-105-0/+49
| | | | | | | | | | | | | | | Gen7+ SURFACE_STATE is different from Gen4-6, so we need separate per-generation functions for creating and updating it. However, the usage is the same, and callers just want to utilize the appropriate functions with minimal pain. So, put them in the vtable. Since these take a brw_context pointer and are only used on Gen4, just add a forward declaration. This is the simplest (if not cleanest) solution. It would be nicer to have a i965-specific vtable, but that's a refactor for another day. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* r600g: don't set the query result to 0 after a call to get_query_resultMarek Olšák2011-11-111-2/+0
| | | | get_query_result doesn't reset the result. Only begin_query does.
* r600g: the type of OCCLUSION_PREDICATE result should be booleanMarek Olšák2011-11-113-11/+17
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* mesa: silence uninitialized var warningBrian Paul2011-11-101-1/+1
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* radeon: silence initializer warningsBrian Paul2011-11-102-11/+33
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* draw/llvm: silence uninitialized variable warningsBrian Paul2011-11-101-0/+2
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* radeon: silence unused var warningsBrian Paul2011-11-101-3/+3
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* egl: silence unused var warningBrian Paul2011-11-101-0/+2
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* r600g: implement PIPE_QUERY_OCCLUSION_PREDICATEMarek Olšák2011-11-101-5/+21
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* r300g: fix query result of GPU_FINISHEDMarek Olšák2011-11-101-1/+1
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* r300g: implement PIPE_QUERY_GPU_FINISHEDMarek Olšák2011-11-101-4/+35
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* r300g: implement PIPE_QUERY_OCCLUSION_PREDICATEMarek Olšák2011-11-101-1/+5
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* llvmpipe/u_format: add support for EXT_texture_shared_exponent + ↵Dave Airlie2011-11-103-3/+42
| | | | | | | | | | | EXT_packed_float These two are fairly unique types so add specific cases for decoding them. Passes piglit fbo-clear-format and fbo-generatemipmap-format tests for these two extensions. Signed-off-by: Dave Airlie <[email protected]>
* llvmpipe: add NV_conditional_render support.Dave Airlie2011-11-107-0/+43
| | | | | | | | This ports the softpipe NV_conditional_render support to llvmpipe. This passes the nv_conditional_render-* piglit tests. Signed-off-by: Dave Airlie <[email protected]>
* r600g: remove useless texture barrierMarek Olšák2011-11-101-2/+0
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* r600g: flush the whole context when CS is full, not just hw_contextMarek Olšák2011-11-103-1/+6
| | | | Because we disable render condition in r600_flush, but not in r600_context_flush.
* r600g: turn some CS overflow checks into assertionsMarek Olšák2011-11-102-12/+2
| | | | They're not really exhaustive and not so useful either.
* r600g: put the rest of CS overflow checks in r600_need_cs_spaceMarek Olšák2011-11-103-18/+9
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* r600g: flush caches regardless of render conditionMarek Olšák2011-11-101-5/+5
| | | | What if somebody enables render condition just before we flush...
* r600g: disable render condition at the end of CS, re-enable at the beginningMarek Olšák2011-11-102-0/+19
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* r600g: don't suspend queries if they have already been suspended by blitterMarek Olšák2011-11-101-2/+11
| | | | And add some assertions.
* r600g: properly reserve CS space for queries_suspendMarek Olšák2011-11-103-21/+18
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* r600g: reserve CS space for a draw command in begin_query and render_conditionMarek Olšák2011-11-103-11/+25
| | | | There's no point in emitting those if you can't emit a draw command too.
* r600g: consolidate checking whether CS is fullMarek Olšák2011-11-103-31/+28
| | | | | | This adds a new function r600_need_cs_space. Currently, it's easy to overflow the CS - queries are not counted in. I guess that's not the only case where the driver may crap out.
* radeon: fix tex1d-border2dDave Airlie2011-11-101-31/+33
| | | | | | Fixes pigit test with T wrap usage. Signed-off-by: Dave Airlie <[email protected]>
* radeon: fix 3-coordinate swtcl emissionDave Airlie2011-11-101-0/+8
| | | | | | This fixes mipmap generation on swtcl rv100. Signed-off-by: Dave Airlie <[email protected]>
* swrast: Add support for glReadPixels() to integer types.Eric Anholt2011-11-091-6/+13
| | | | | | | With this change, i965 passes GL_EXT_texture_integer/fbo_integer_precision_clear Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add support for unpacking 32-bit integer formats to int spans.Eric Anholt2011-11-092-0/+128
| | | | | | | | | This is the inverse operation to _mesa_pack_rgba_span_int. The 16-bit code isn't done because of lack of testing and not being sure how sign extension/clamping should be handled between, say, 16-bit int and 32-bit int or uint. Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Add support for glClear() to integer color buffers.Eric Anholt2011-11-091-4/+109
| | | | | | | | | | This requires using a new fragment shader to get the integer color output, and a new vertex shader because #version has to match between the two. v2: Clarify that there's no need for BindFragDataLocation. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965: Claim to support rendering to integer FBOs.Eric Anholt2011-11-092-1/+13
| | | | | | | | | | | | We're missing support for the software paths still, but basic rendering is working. v2: Override RGB_INT32/UINT32 to not be renderable, since the hardware can't do it but we do allow texturing from it now. Drop the DataType override, since the _mesa_problem() isn't in that path any more. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965/fs: Add support for user-defined out variables.Eric Anholt2011-11-092-35/+39
| | | | | | | | | | | | Before, I was tracking the ir_variable * found for gl_FragColor or gl_FragData[]. Instead, when visiting those variables, set up an array of per-render-target fs_regs to copy the output data from. This cleans up the color emit path, while making handling of multiple user-defined out variables easier. v2: incorporate idr's feedback about ir->location (changes by Kenneth Graunke) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Preserve the source register type when doing color writes.Eric Anholt2011-11-091-4/+7
| | | | | | | When rendering to integer color buffers, we need to be careful to use MRFs of the correct type when emitting color writes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make brw_type_for_base_type return the element type for arrays.Eric Anholt2011-11-091-0/+1
| | | | | | | | | | | | | | | | Previously, brw_type_for_base_type returned UD for array variables, similar to structures. For structures, each field may have a different type, so every field access must explicitly override the register's type with that field's type. We chose to return UD in this case since it was the least common, so errors would be more obvious. For arrays, it makes far more sense to return the type corresponding to an element of the array. This allows normal array access to work without the hassle of explicitly overriding the register's type. This should obsolete a bunch of type overrides throughout the code. Reviewed-by: Kenneth Graunke <[email protected]>
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