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* ilo: add GEN7 GPEChia-I Wu2013-04-263-0/+2367
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* ilo: add GEN6 GPEChia-I Wu2013-04-265-0/+5270
| | | | | GEN6 GPE (Graphics Processing Engine) is a low-level interface to emit 3D commands and states.
* ilo: hook up pipe context query functionsChia-I Wu2013-04-262-5/+208
| | | | None of the query types are supported yet.
* ilo: hook up pipe context transfer functionsChia-I Wu2013-04-261-4/+239
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* ilo: hook up pipe context blit functionsChia-I Wu2013-04-263-5/+269
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* ilo: hook up pipe context state functionsChia-I Wu2013-04-264-61/+1148
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* ilo: add functions to manage shadersChia-I Wu2013-04-264-0/+899
| | | | | This commits add shader cache, shader state, shader variant, and etc. It does not add the shader compiler though.
* ilo: hook up pipe context flush functionChia-I Wu2013-04-262-1/+79
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* ilo: add command parserChia-I Wu2013-04-263-0/+649
| | | | The command parser manages batch buffers and command submissions.
* ilo: hook up pipe screen resource functionsChia-I Wu2013-04-262-5/+856
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* ilo: hook up pipe screen format functionsChia-I Wu2013-04-262-2/+683
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* ilo: hook up pipe_screen param and fence functionsChia-I Wu2013-04-263-11/+606
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* ilo: add debug flags settable through ILO_DEBUGChia-I Wu2013-04-262-0/+28
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* ilo: new pipe driver for Intel GEN6+Chia-I Wu2013-04-2628-0/+4887
| | | | | This commit adds some boilerplate code. The header files found under include/ are copied from i965.
* winsys/intel: new winsys for intelChia-I Wu2013-04-265-0/+946
| | | | | This is a wrapper for libdrm_intel to allow the pipe driver to stay OS agnostic.
* gallivm: Fix trivial out-of-bounds indirection in lp_build_cube_lookup().José Fonseca2013-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Courtesy of clang: src/gallium/auxiliary/gallivm/lp_bld_sample.c:1483:10: warning: array index of '2' indexes past the end of an array (that contains 2 elements) [-Warray-bounds] tmp[2] = lp_build_swizzle_aos(coord_bld, ddx_ddy[1], swizzle02); ^ ~ src/gallium/auxiliary/gallivm/lp_bld_sample.c:1430:10: note: array 'tmp' declared here LLVMValueRef ddx_ddy[2], tmp[2], rho_vec; ^ src/gallium/auxiliary/gallivm/lp_bld_sample.c:1487:56: warning: array index of '2' indexes past the end of an array (that contains 2 elements) [-Warray-bounds] rho_vec = lp_build_add(coord_bld, rho_vec, tmp[2]); ^ ~ src/gallium/auxiliary/gallivm/lp_bld_sample.c:1430:10: note: array 'tmp' declared here LLVMValueRef ddx_ddy[2], tmp[2], rho_vec; ^ src/gallium/auxiliary/gallivm/lp_bld_sample.c:1491:56: warning: array index of '2' indexes past the end of an array (that contains 2 elements) [-Warray-bounds] rho_vec = lp_build_max(coord_bld, rho_vec, tmp[2]); ^ ~ src/gallium/auxiliary/gallivm/lp_bld_sample.c:1430:10: note: array 'tmp' declared here LLVMValueRef ddx_ddy[2], tmp[2], rho_vec; ^
* i965/vs: Add support for LRP instruction.Matt Turner2013-04-255-3/+22
| | | | | | | | | | Only 13 affected programs in shader-db, but they were all helped. total instructions in shared programs: 368877 -> 368851 (-0.01%) instructions in affected programs: 1576 -> 1550 (-1.65%) Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Add a function to fix-up uniform arguments for 3-src insts.Matt Turner2013-04-252-0/+25
| | | | | | | | | | | | | | | | | Three-source instructions have a vertical stride overloaded to 4, which prevents directly using vec4 uniforms as arguments. Instead we need to insert a MOV instruction to do the replication for the three-source instruction. With this in place, we can use three-source instructions in the vertex shader. While some thought needs to go into deciding whether its better to use a three-source instruction rather than a sequence of equivalent instructions (when one or more sources are uniforms or immediates), this will allow us to skip a lot of ugly lowering code and use the BFE and BFI2 instructions directly. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* winsys/radeon: consolidate tracing into winsys v2Jerome Glisse2013-04-2516-95/+68
| | | | | | | | | | | | This move the tracing timeout and printing into winsys and add an debug environement variable for it (R600_DEBUG=trace_cs). Lot of file touched because of winsys API changes. v2: Do not write lockup file if ib uniq id does not match last one Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Removed unused and untested codeTom Stellard2013-04-255-776/+66
| | | | | | | | There was a lot of code in evergreen_compute_internal.c that was not being used at all and most of it was duplicating code from other parts of the driver. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Use a constant buffer to store kernel parameters v2Tom Stellard2013-04-252-16/+30
| | | | | | | | | v2: - Fix usage of set_constant_buffer() - Fix typo in comment Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add evergreen_emit_cs_constant_buffers() v2Tom Stellard2013-04-253-11/+36
| | | | | | | | v2: - Bump R600_NUM_ATOMS Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Don't use radeon_winsys::buffer_wait() after dispatching a kernelTom Stellard2013-04-251-6/+0
| | | | | | | The state tracker should be responsible for waiting for the kernel to finish. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Fix input buffer size calculationTom Stellard2013-04-251-1/+1
| | | | | | Buffer size should be in bytes not dwords. Reviewed-by: Alex Deucher <[email protected]>
* linux: Don't emit a .note.ABI-tag section anymore (#26663)Adam Jackson2013-04-254-52/+0
| | | | | | | | | | | We don't support pre-2.6 kernels anyway - the install docs say 2.6.28 for DRI - and apparently this confuses ld.so's sorting when multiple libGLs are installed. Just remove it. Note: this is a candidate for the stable branches. Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* freedreno: use writecombine buffersRob Clark2013-04-251-1/+2
| | | | | | | Better than uncached for writes, which are common for vertex buffer upload, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno: don't patch and re-emit same shader as muchRob Clark2013-04-255-64/+65
| | | | | | | | New textures or vertex buffers don't always require patching and re-emitting the shaders. So do a better job of figuring out when we actually have to patch the shader. Signed-off-by: Rob Clark <[email protected]>
* i965: Avoid recompiles for fragment clamping on non-clamping APIs.Eric Anholt2013-04-252-2/+2
| | | | | | | | | | Removes 75/78 state-dependent recompiles in GLB2.7 (the remaining 3 are due to FBO-rendering size predictions). We currently expose GL_ARB_color_buffer_float on GL core, so we may mis-predict there, but I'm about to send a patch for removing that silly extension in that case. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* draw: Yield zeros for LLVM fetches of non-existing vertex elements.José Fonseca2013-04-251-21/+28
| | | | | | | If a bug in an app/stater-tacker causes vertex buffer to fetch vertex elements that are not bound, simply return zeros instead of crashing. Reviewed-by: Brian Paul <[email protected]>
* trace: Only close trace files on exit.José Fonseca2013-04-253-18/+4
| | | | | | Many applications don't exit cleanly, others may create and destroy a screen multiple times, so we only write </trace> tag and close at exit time.
* graw: Set the vertex shader constant buffer.José Fonseca2013-04-251-1/+1
| | | | We were setting the fragment shader, which wasn't needed.
* graw: Simple utilities to dump and disassemble TGSI tokens.José Fonseca2013-04-253-0/+97
| | | | | Useful for core dumps, where calling tgsi_dump() from gdb is not an alternative.
* scons: Support clang.José Fonseca2013-04-253-3/+5
| | | | | | | | | | | clang is supports most gcc options / extensions, with a some exceptions. The biggest advantage of using clang is that compilation times are much short. One can tell scons to use clang when building by invoking it as CC=clang CXX=clang++ scons libgl-xlib
* util/u_sse: Fix _mm_shuffle_epi8 prototype for clang.José Fonseca2013-04-251-1/+6
| | | | | Clang does not support __artificial__. Instead match precisely what's in the clang headers.
* scons: Remove redundant code.José Fonseca2013-04-251-3/+0
| | | | -fvisibility=hidden is already elsewhere for the whole tree.
* mesa: fix bogus comment about PrimitiveRestart fieldsChris Forbes2013-04-251-2/+2
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: report correct sample positionsChris Forbes2013-04-251-4/+4
| | | | | | | | | From low to high bits, the sample positions are packed y0,x0,y1,x1... Fixes arb_texture_multisample-sample-position piglit. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* freedreno: fix bogus IMM const reg indexRob Clark2013-04-242-3/+3
| | | | | | | | We were assigning incorrect const register for immediates, and potentially writing immediate const to the wrong location. This fixes an incorrect-rendering bug with xonotic. Signed-off-by: Rob Clark <[email protected]>
* freedreno: clear fixes and debuggingRob Clark2013-04-244-1/+29
| | | | | | | | Set a few extra registers to make sure we are in proper state for clearing. And also add some debug options to mark all state dirty in clear and gmem operations to aid in debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix texture fetch typeRob Clark2013-04-244-2/+10
| | | | | | | There is a bit we need to set for 2D vs 3D fetch, to tell the hw whether there are two or there valid input components. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix temp register usageRob Clark2013-04-241-48/+52
| | | | | | | | | | | | | | | The previous approach of using the dst register as an intermediate temporary doesn't work in a lot of cases. For example, if the dst register is the same as one of the src registers. For now, just simplify it and always allocate a new register to use as an intermediate. In some cases this will result in more registers used than required. I think the best solution would be to implement an optimization pass to reduce the number of registers used, which would also solve the problem we have now of not being able to use GPRs that are assigned for TGSI_FILE_INPUT. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add noop driverRob Clark2013-04-241-1/+3
| | | | | | It is useful for debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno: use u_math macros/helpers moreRob Clark2013-04-246-25/+20
| | | | | | | | | Get rid of a few self-defined macros: ALIGN() -> align() min() -> MIN2() max() -> MAX2() Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement fd_screen_destroy()Rob Clark2013-04-241-6/+26
| | | | | | | | Opps, didn't notice that I had left it stubbed out. Also, make things fail a bit more gracefully when things go wrong. Signed-off-by: Rob Clark <[email protected]>
* freedreno: set SWAP bit based on formatRob Clark2013-04-241-7/+19
| | | | | | | | Really this should be set based on buffer format, not on color vs depth/stencil. Probably there should be more formats that set the bit as we add support for more render target formats. Signed-off-by: Rob Clark <[email protected]>
* radeon/llvm: Fix segfault with a specifc libelf implementationTom Stellard2013-04-241-0/+4
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html requires calling elf_version() prior to calling elf_memory() Tested-by: Michel Dänzer <[email protected]>
* r600g: use CP DMA for buffer clears on evergreen+Alex Deucher2013-04-244-2/+119
| | | | | | | | | | Lighter weight then using streamout. Only evergreen and newer asics support embedded data as src with CP DMA. Reviewed-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* i965/gen7: fix encoding of (huge) surface size for BRW_SURFACE_BUFFERChia-I Wu2013-04-241-6/+10
| | | | | | | | | | | | | | | | | | Unlike GEN6, the bits of entry count are distributed like this width = (entry_count & 0x0000007f); /* bits [6:0] */ height = (entry_count & 0x001fff80) >> 7; /* bits [20:7] */ depth = (entry_count & 0x7fe00000) >> 21; /* bits [30:21] */ The maximum entry count is still limited to 2^27. This was noted while going over the PRM. No test is impacted, because 1<<20 (the bit that moved) is much larger than GL_UNIFORM_BLOCK_MAX_SIZE, GL_MAX_TEXTURE_BUFFER_SIZE, or MAX_*_UNIFORM_COMPONENTS. v2: Explain more in the commit message (by anholt) Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: fix 3DSTATE_LINE_STIPPLE_PATTERNChia-I Wu2013-04-241-3/+14
| | | | | | | | | | The inverse repeat count should taks up bits 31:15 and is in U1.16. Fixes the "Restarting lines within a single Begin/End block" subtest of piglit linestipple, and gets the other failing subtests much closer to passing. v2: Rewrite commit message with more detailed piglit info (by anholt) Reviewed-by: Eric Anholt <[email protected]>
* i965: fix SURFACE_STATE dumpingChia-I Wu2013-04-241-4/+4
| | | | | | Wrong fields were used when dumping width and height. Reviewed-by: Eric Anholt <[email protected]>
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