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* i965: Clean up stale NDC comment.Eric Anholt2008-11-031-2/+1
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* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-031-3/+3
| | | | This cuts one MOV out when setting a zero header.
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-039-25/+24
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-031-3/+7
| | | | Also, add a comment explaining what brw->urb.constrained tries to do.
* gallium: WinCE portability fixes.José Fonseca2008-11-032-2/+39
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* gallium: Fix typo.José Fonseca2008-11-031-1/+1
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* softpipe: Don't call pipe_buffer_destroy directly.José Fonseca2008-11-032-2/+2
| | | | Use pipe_buffer_reference instead.
* pipebuffer: Ensure refcounts of live buffer objects are never zero.José Fonseca2008-11-032-5/+13
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* gallium: Ensure refcounts of live objects are never zero.José Fonseca2008-11-031-12/+18
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* gallium: Fix msvc warning.José Fonseca2008-11-031-1/+1
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* Merge commit 'origin/master' into gallium-0.2Alan Hourihane2008-11-0151-2883/+3453
|\ | | | | | | | | | | Conflicts: src/mesa/shader/slang/library/slang_vertex_builtin_gc.h
| * mesa: silence warningsBrian Paul2008-11-011-3/+3
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| * mesa: do scope replacement for while/for loops tooBrian Paul2008-11-011-3/+7
| | | | | | | | This fixes a function inlining bug involving vars declared inside loop bodies.
| * mesa: glsl tree print improvementsBrian Paul2008-11-011-1/+17
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| * mesa: fix assignment / parameter passing of sampler typesBrian Paul2008-11-013-8/+29
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| * mesa: additional debug flags for glsl debug/disassemblyBrian Paul2008-11-014-53/+53
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| * Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <[email protected]>
| * mesa: fix some bugs with precision qualifier parsingBrian Paul2008-10-319-2382/+2459
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| * mesa: do scope replacement for variable initializers tooBrian Paul2008-10-311-0/+11
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| * mesa: fix copy/paste error in GLSL error msgBrian Paul2008-10-311-1/+1
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| * intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt2008-10-311-5/+1
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| * intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX)Eric Anholt2008-10-311-7/+0
| | | | | | | | | | GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage.
| * intel: Add more fallback debugging for glDrawPixels.Eric Anholt2008-10-311-8/+33
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| * i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
| | | | | | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
| * i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
| | | | | | | | This is required for scatter writes in destination regions to work.
| * mesa: fix a typo in the previous commitXiang, Haihao2008-10-311-1/+1
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| * mesa: fix an issue in _mesa_PointParameterfv().Xiang, Haihao2008-10-301-1/+1
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| * intel: Fix glDrawPixels with 4d RasterPos.Eric Anholt2008-10-281-4/+9
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| * i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
| | | | | | | | | | | | | | | | Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
| * mesa: fix stand-alone glslcompiler buildBrian Paul2008-10-281-6/+2
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| * intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt2008-10-2817-292/+272
| | | | | | | | | | | | | | This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
| * i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-282-3/+7
| | | | | | | | | | This is required for threads to be spawned with correctly sized GRF register blocks.
| * i965: Fix compiler warning from unused var.Eric Anholt2008-10-271-1/+0
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| * i965: Remove dead brw->wrap flag.Eric Anholt2008-10-273-6/+0
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| * intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.Eric Anholt2008-10-271-26/+17
| | | | | | | | | | | | Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL, which needs a handle, and failing. None of our buffers were tiled yet, but they will be at some point with DRI2 and UXA.
* | CELL: fix use of stencil value maskRobert Ellison2008-10-301-42/+112
| | | | | | | | | | | | | | The Cell stencil tests were completely ignoring the stencil value mask. Now the original code paths are still used if the stencil value mask is all 1s; but code to use the mask for the stencil value and reference value comparisons is now emitted if the mask is not all 1s.
* | gallivm: replace the temp parameters of the JIT function with alloca'ed ↵Stephane Marchesin2008-10-304-30/+41
| | | | | | | | temps. This avoids useless writes of temporary results.
* | cell: Protected use of non-initialized untile buffersJonathan White2008-10-301-4/+7
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* | CELL: stencil bug fixesRobert Ellison2008-10-305-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two definitive bugs in stenciling were fixed. The first, reversed registers in the generated Select Bytes (selb) instruction, caused the stenciling INCR and DECR operations to fail dramatically, putting new values in where old values were supposed to be and vice versa. The second caused stencil tiles to not be read and written from main memory by the SPUs. A per-spu flag, spu.read_depth, was used to indicate whether the SPU should be reading depth tiles, and was set only when depth was enabled. A second flag, spu.read_stencil, was set when stenciling was enabled, but never referenced. As stenciling and depth are in the same tiles on the Cell, and there is no corresponding TAG_WRITE_TILE_STENCIL to complement TAG_WRITE_TILE_COLOR and TAG_WRITE_TILE_Z, I fixed this by eliminating the unused "spu.read_stencil", renaming "spu.read_depth" to "spu.read_depth_stencil", and setting it if either stenciling or depth is enabled. I also added an optimization to the fragment ops generation code, that avoids calculating stencil values and/or stencil writemask when the stencil operations are all KEEP.
* | cell: Added check for PIPE_FLUSH_RENDER_CACHE to cell_flush to fix black ↵Jonathan White2008-10-301-1/+1
| | | | | | | | blocks during st_readpixels due to a flush wait not happening in order to allow any previous rendering to complete.
* | gallium: grow SPE instruction buffer as neededBrian Paul2008-10-291-16/+41
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* | gallium: no longer pass max_inst to ppc_init_func()Brian Paul2008-10-293-3/+3
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* | gallium: use execmem for PPC code, grow instruction buffer as neededBrian Paul2008-10-293-21/+58
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* | gallium: fix alignment parameter passed to u_mmAllocMem()Brian Paul2008-10-291-2/+2
| | | | | | | | | | | | Was 32, now 5. The param is expressed as a power of two exponent. The net effect is that the alignment was a no-op on X86 but on PPC we always got the same memory address everytime rtasm_exec_malloc() was called.
* | gallium: prefix memory manager functions with u_ to differentiate from ↵Brian Paul2008-10-294-21/+21
| | | | | | | | functions in mesa/main/mm.c
* | gallium: test for PIPE_OS_LINUX instead of __linux__Brian Paul2008-10-291-4/+5
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* | cell: add scalar param to emit_function_call() to indicate scalar function callsBrian Paul2008-10-291-34/+69
| | | | | | | | | | Scalar calls only use the X component of the src regs and smear the result across the dest register's X/Y/Z/W.
* | cell: use simd utilities for pow, exp2, log2Brian Paul2008-10-291-22/+6
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* | gallium: added PPC support for SWZ, XPD, POWBrian Paul2008-10-291-0/+86
| | | | | | | | That's the last of the ARB_v_p opcodes, except for ARL.
* | gallium: clean-upsBrian Paul2008-10-291-10/+4
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