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* Merge branch 'drm-gem'Eric Anholt2008-08-0876-4312/+1748
|\ | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_span.c src/mesa/main/fbobject.c This converts the i915 driver to use the GEM interfaces for object management.
| * intel-gem: Update to new check_aperture API for classic mode.Eric Anholt2008-08-0831-305/+245
| | | | | | | | | | | | To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
| * 965: cleanups to state emission from aperture checking and state ordering.Eric Anholt2008-08-084-46/+3
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| * intel-gem: Always build GEM execbuffer code.Eric Anholt2008-07-311-11/+0
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| * intel-gem: Use new getparam to detect kernel GEM support.Eric Anholt2008-07-301-1/+8
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| * intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.Eric Anholt2008-07-262-0/+72
| | | | | | | | | | Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't actually been tested.
| * Merge branch 'master' into drm-gemIan Romanick2008-07-25199-30703/+8739
| |\ | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.c src/mesa/drivers/dri/i965/brw_wm_surface_state.c
| * | mesa: Return 0 for cube map face of non-cubemap framebuffer attachments.Eric Anholt2008-07-251-1/+4
| | | | | | | | | | | | Fixes some oglconform fbo testcases.
| * | intel: If a tex image doesn't fit in the object's tree, make a temporary tree.Eric Anholt2008-07-251-3/+18
| | | | | | | | | | | | | | | | | | | | | Previously, we would just store the data as malloced memory hanging off the object, which would get memcpyed in at validate time. This broke an oglconform render-to-texture test, since validate wasn't called but a miptree was expected.
| * | intel: Add a little span cache to spead up readpixels by cutting syscalls.Eric Anholt2008-07-233-12/+42
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| * | intel-gem: Use pread/pwrite for span access.Eric Anholt2008-07-234-197/+141
| | | | | | | | | | | | | | | This will avoid clflushing entire buffers for small acesses, such as those commonly used by regression tests.
| * | intel: improve 2d batchbuffer debug output.Eric Anholt2008-07-231-8/+14
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| * | intel: Fix CopyTexSubImage's src tiling arg for the blit.Eric Anholt2008-07-231-1/+1
| | | | | | | | | | | | Didn't hurt 915, but needed for 965.
| * | intel: move renderbuffer mapping to separate functions.Eric Anholt2008-07-233-107/+80
| | | | | | | | | | | | | | | | | | | | | This lets us avoid duplicated code for doing so, including the depthstencil paths that aren't covered by SpanRenderStart/Finish. Those paths were missing the span funcs setup, leading to a null dereference in the fbotexture demo.
| * | intel-gem: Bump driver dateIan Romanick2008-07-181-3/+7
| | | | | | | | | | | | | | | Bump the driver date and insert the string "GEM". When running tests, this make it much easier to know that the right driver is being used.
| * | Remove redundant initalization of MaxTextureUnitsIan Romanick2008-07-161-1/+0
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| * | intel-gem: Disable spantmp sse/mmx functions when tile swizzling.Eric Anholt2008-07-152-3/+17
| | | | | | | | | | | | | | | | | | | | | Those functions rely on being able to treat the GET_PTR returned value as an array indexed by x, but that's not the case for our tiling. Bug #16387
| * | i915: fix build after previous commit.Eric Anholt2008-07-141-1/+1
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| * | drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt2008-07-1118-298/+250
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| * | intel: span rendering requires just a flush before starting, not finish.Eric Anholt2008-07-021-1/+1
| | | | | | | | | | | | The dri_bo_map()s that follow will take care of idling the hardware as needed.
| * | intel-gem: Emit an MI_FLUSH at glFlush() so frontbuffer rendering is flushed.Eric Anholt2008-07-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | We have something similar in the X Server that covers X Server rendering, this is the equivalent here for rendering to the front buffer. If we cared about avoiding this at glFlush time, we could only do this when some actual frontbuffer rendering had occurred. Bug #16392.
| * | intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt2008-07-021-0/+10
| | | | | | | | | | | | | | | Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly.
| * | intel-gem: Fix Y-tiling span setup.Eric Anholt2008-07-026-27/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
| * | intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt2008-07-014-18/+46
| | | | | | | | | | | | | | | | | | It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect.
| * | intel: Fix locking when doing intel_region_cow().Eric Anholt2008-06-261-2/+2
| | | | | | | | | | | | | | | This was broken in the merge of 965 blit support. It tried to lock only when things were already locked.
| * | intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.Eric Anholt2008-06-2613-112/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
| * | Merge commit 'origin/master' into drm-gemEric Anholt2008-06-2492-998/+422
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| * | | i915: Accumulate the VB into a local buffer and subdata it in.Eric Anholt2008-06-237-31/+48
| | | | | | | | | | | | | | | | This lets GEM use pwrite, for an additional 4% or so speedup.
| * | | i915: Convert to using VBs instead of inline prims.Eric Anholt2008-06-239-214/+299
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| * | | i915: Note the non-PBO fallback for textured drawpixels under DEBUG_PIXEL.Eric Anholt2008-06-181-1/+2
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| * | | i915: Restore the accelerated PBO pixel path functions after GEM changes.Eric Anholt2008-06-185-24/+5
| | | | | | | | | | | | | | | | | | | | The fencing code is not required, and waiting on the fences defeated one of the purposes of the extension, which is to allow asynchronous readpixels.
| * | | Merge commit 'origin/master' into drm-gemEric Anholt2008-06-1886-9683/+11737
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| * | | | [intel] Fix no_rast option on non-965.Eric Anholt2008-06-173-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The no_rast fallback was getting partially overwritten by later TNL init, resulting in a segfault when things were in a mixed-up state.
| * | | | [intel-gem] Bug #16326: Fix X tile unswizzling on 965.Eric Anholt2008-06-171-0/+26
| | | | | | | | | | | | | | | | | | | | Apparently a bit gets flipped in the addressing for some rows of each tile.
| * | | | [intel-gem] Chase domain flag renaming in the DRM.Eric Anholt2008-06-1114-41/+41
| | | | | | | | | | | | | | | | | | | | This is an API breakage only.
| * | | | [gem] Enable bo_reuse by default.Eric Anholt2008-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The objects are swappable, so we're less concerned by excessive object allocation now, and it's about a 20% performance improvement. If we get concerns about the memory consumption from others, we can look into a compromise position later.
| * | | | [intel-gem] Call the new throttle ioctl from swap buffersKeith Packard2008-06-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Swap buffers is a fairly reasonable time to wait for the hardware for a while; this keeps us from overrunning the ring.
| * | | | Merge commit 'origin/master' into drm-gemKeith Packard2008-06-03141-19948/+8393
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.h src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h src/mesa/drivers/dri/intel/intel_ioctl.c
| * | | | | [intel] Convert drivers to using libdrm bufmgr code.Eric Anholt2008-06-0335-3737/+105
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| * | | | | [intel-gem] Remember last offset of reused BOs to avoid more kernel relocs.Eric Anholt2008-05-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is good for about 5% on ipers on 965, and should help any cpu-bound app.
| * | | | | [intel-gem] Once mapped, leave buffers mapped.Keith Packard2008-05-281-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mapping and unmapping buffers is expensive, and having the map around isn't harmful (other than consuming address space). So, once mapped, just leave buffers mapped in case they get re-used.
| * | | | | [intel] all flushing in intelEmitCopyBlitKeith Packard2008-05-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add both MI_FLUSH and intel_batchbuffer_flush to intelEmitCopyBlit. This ensures that the data are flushed *and* the gem kernel driver sees the various memory domain transitions.
| * | | | | [intel] Enable buffer re-use for gemKeith Packard2008-05-251-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new DRM_IOCTL_I915_GEM_BUSY ioctl to detect idle buffers for re-use.
| * | | | | Remove stale comment about glFlush().Eric Anholt2008-05-231-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need an MI_FLUSH there, because everything that's been flushed in the batch will eventually hit the hardware.
| * | | | | Emit a flush after the swapbuffers blit, so contents end up on the screen.Eric Anholt2008-05-235-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, since the MI_FLUSH at the end of every batch had been removed, non-automatic-flushing chips (965) wouldn't get flushed and apps with static rendering would get partial screen contents until the server's blockhandler flush kicked in.
| * | | | | Add back a mostly-correct glFinish for GEM and fake.Eric Anholt2008-05-225-4/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The right solution would probably be keeping a list of regions which have been rendered to.
| * | | | | [intel-gem] Make sure set_domain is called often enough.Keith Packard2008-05-221-31/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The write_domain needs to be set after any batch buffer uses an object, track when that happens in the new 'cpu_domain_set' field.
| * | | | | [intel-gem] Don't calloc reloc buffersKeith Packard2008-05-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only a few relocations are typically used, so don't clear the whole thing.
| * | | | | [GEM] Actually include the presumed offset in initial relocations.Eric Anholt2008-05-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This avoids kernel relocations for most batchbuffer relocs.
| * | | | | [intel] update GEM api. Add bo_subdata and bo_get_subdata driver hooks.Keith Packard2008-05-115-68/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Track DRM GEM name changes. Add driver hooks for bo_subdata and bo_get_subdata so that GEM can use pread and pwrite.
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