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* swr/rast: Add vgather to x86 lowering pass.George Kyriazis2018-04-181-9/+76
| | | | | | Add support for generic VGATHERPD intrinsic in x86 lowering pass. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: fix commentGeorge Kyriazis2018-04-181-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: add cvt instructions in x86 lowering passGeorge Kyriazis2018-04-185-59/+48
| | | | | | Support generic VCVTPD2PS and VCVTPH2PS in x86 lowering pass. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix alloca usage in jitterGeorge Kyriazis2018-04-183-0/+20
| | | | | | | | Fix issue where temporary allocas were getting hoisted to function entry unnecessarily. We now explicitly mark temporary allocas and skip hoisting during the hoist pass. Shuold reduce stack usage. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Change gfx pointers to gfxptr_tGeorge Kyriazis2018-04-1811-103/+220
| | | | | | | Changing type to gfxptr for indices and related changes to fetch and mem builder code. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix byte offset for non-indexed drawsGeorge Kyriazis2018-04-181-2/+3
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add support for setting optimization levelGeorge Kyriazis2018-04-189-18/+55
| | | | | | for JIT compilation Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Adding translate call to builder_gfx_mem.George Kyriazis2018-04-182-0/+7
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix codegen for typedef typesGeorge Kyriazis2018-04-181-0/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: add x86 lowering pass to fragment shaderGeorge Kyriazis2018-04-181-0/+7
| | | | | | | | Needed because some FP paths (namely stipple) use gather intrinsics that now need to be lowered to x86. v2: fix typo in commit message Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Enable generalized fetch jitGeorge Kyriazis2018-04-185-1103/+139
| | | | | | | | | Enable generalized fetch jit with 8 or 16 wide SIMD target. Still some work needed to remove some simd8 double pumping for 16-wide target. Also removed unused non-gather load vertices path. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add builder_gfx_mem.{h|cpp}George Kyriazis2018-04-185-4/+210
| | | | | | | | | Abstract usage scenarios for memory accesses into builder_gfx_mem. Builder_gfx_mem will convert gfxptr_t from 64-bit int to regular pointer types for use by builder_mem. v2: reworded commit message; renamed enum more appropriately Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Lower VGATHERPS and VGATHERPS_16 to x86.George Kyriazis2018-04-181-67/+2
| | | | | | | Some more work to do before we can support simultaneous 8-wide and 16-wide and remove the VGATHERPS_16 version. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Cleanup of JitManager convenience typesGeorge Kyriazis2018-04-184-44/+5
| | | | | | | Small cleanup. Remove convenience types from JitManager and standardize on the Builder's convenience types. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Lower PERMD and PERMPS to x86.George Kyriazis2018-04-184-86/+14
| | | | | | | Add support for providing an emulation callback function for arch/width combinations that don't map cleanly to an x86 intrinsic. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Start refactoring of builder/packetizer.George Kyriazis2018-04-1816-46/+565
| | | | | | | | | | | Move x86 intrinsic lowering to a separate pass. Builder now instantiates generic intrinsics for features not supported by llvm. The separate x86 lowering pass is responsible for lowering to valid x86 for the target SIMD architecture. Currently it's a port of existing code to get it up and running quickly. Will eventually support optimized x86 for AVX, AVX2 and AVX512. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Simplify #define usage in gen source fileGeorge Kyriazis2018-04-181-4/+3
| | | | | | | | | | | | Removed preprocessor defines from structures passed to LLVM jitted code. The python scripts do not understand the preprocessor defines and ignores them. So for fields that are compiled out due to a preprocessor define the LLVM script accounts for them anyway because it doesn't know what the defines are set to. The sanitize defines for open source are fine in that they're safely used. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Move CallPrint() to a separate fileGeorge Kyriazis2018-04-184-21/+56
| | | | | | Needed work for jit code debug. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix name mangling for LLVM pow intrinsicGeorge Kyriazis2018-04-181-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add some archrast countersGeorge Kyriazis2018-04-187-4/+53
| | | | | | Hook up archrast counters for shader stats: instructions executed. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Code cleanupGeorge Kyriazis2018-04-181-8/+1
| | | | | | Removing some code that doesn't seem to do anything meaningful. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add "Num Instructions Executed" stats intrinsic.George Kyriazis2018-04-181-7/+21
| | | | | | | Added a SWR_SHADER_STATS structure which is passed to each shader. The stats pass will instrument the shader to populate this. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add MEM_ADD helper function to Builder.George Kyriazis2018-04-182-0/+9
| | | | | | | | mem[offset] += value This function will be heavily used by all stats intrinsics. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Permute work for simd16George Kyriazis2018-04-187-10/+67
| | | | | | | | Fix slow permutes in PA tri lists under SIMD16 emulation on AVX Added missing permute (interlane, immediate) to SIMDLIB Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: WIP builder rewrite (2)George Kyriazis2018-04-181-4/+13
| | | | | | | | | | | | | Finish up the remaining explicit intrinsic uses. At this point all explicit Intrinsic::getDeclaration() usage has been replaced with auto generated macros generated with gen_llvm_ir_macros.py. Going forward, make sure to only use the intrinsics here, adding new ones as needed. Next step is to remove all references to x86 intrinsics to keep the builder target-independent. Any x86 lowering will be handled by a separate pass. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add autogen of helper llvm intrinsics.George Kyriazis2018-04-1813-126/+130
| | | | | | | | Replace sqrt, maskload, fp min/max, cttz, ctlz with llvm equivalent. Replace AVX maskedstore intrinsic with LLVM intrinsic. Add helper llvm macros for stacksave, stackrestore, popcnt. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: WIP builder rewrite.George Kyriazis2018-04-182-14/+0
| | | | | | Start removing avx2 macros for functionality that exists in llvm. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: LLVM 6 fixGeorge Kyriazis2018-04-181-1/+1
| | | | | | for getting masked gather intrinsic (also compatible with LLVM 4) Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Changes to allow jitter to compile with LLVM5George Kyriazis2018-04-181-1/+17
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add some archrast statsGeorge Kyriazis2018-04-189-11/+105
| | | | | | | | | Add stats for degenerate and backfacing primitive counts Wire archrast stats for alpha blend and alpha test. pass value to jitter, upon return have archrast event increment a value Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Silence some unused variable warningsGeorge Kyriazis2018-04-181-1/+11
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add debug type info for i128George Kyriazis2018-04-181-0/+1
| | | | | | Help support debug info in 16 wide shaders. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Use blend context struct to pass paramsGeorge Kyriazis2018-04-183-49/+62
| | | | | | | Stuff parameters into a blend context struct before passing down through the PFN_BLEND_JIT_FUNC function pointer. Needed for stat changes. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Introduce JIT_MEM_CLIENTGeorge Kyriazis2018-04-183-40/+71
| | | | | | | Add assert for correct usage of memory accesses v2: reworded commit message; renamed enum more appropriately Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add some instructions to jitterGeorge Kyriazis2018-04-183-0/+15
| | | | | | VPHADDD, PMAXUD, PMINUD Reviewed-by: Bruce Cherniak <[email protected]>
* meson: Version libMesaOpenCL like autotools doesJan Alexander Steffens (heftig)2018-04-171-2/+2
| | | | | | | | | | | This is for parity with autotools. It names the library libMesaOpenCL.so.1.0.0 and points mesa.icd to the .1 symlink. opencl_version now matches configure.ac's OPENCL_VERSION. Signed-off-by: Jan Alexander Steffens (heftig) <[email protected]> Tested-By: Aaron Watry <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: Add library versions to swr driversJan Alexander Steffens (heftig)2018-04-171-0/+4
| | | | | | | This is for parity with autotools. Signed-off-by: Jan Alexander Steffens (heftig) <[email protected]> Acked-by: Dylan Baker <[email protected]>
* radv: fix scissor computation when using half-pixel viewport offsetSamuel Pitoiset2018-04-171-4/+4
| | | | | | | | | | | 'scale[i]' can be non-integer. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074 Fixes: 0f3de89a56a ("radv: Use the guard band.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Niuwenhuizen <[email protected]>
* spirv: Accept doubles in FaceForward, Reflect and RefractNeil Roberts2018-04-171-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | The SPIR-V spec doesn’t specify a size requirement for these and the equivalent functions in the GLSL spec have explicit alternatives for doubles. Refract is a little bit more complicated due to the fact that the final argument is always supposed to be a scalar 32- or 16- bit float regardless of the other operands. However in practice it seems there is a bug in glslang that makes it convert the argument to 64-bit if you actually try to pass it a 32-bit value while the other arguments are 64-bit. This adds an optional conversion of the final argument in order to support any type. These have been tested against the automatically generated tests of glsl-4.00/execution/built-in-functions using the ARB_gl_spirv branch which tests it with quite a large range of combinations. The issue with glslang has been filed here: https://github.com/KhronosGroup/glslang/issues/1279 v2: Convert the eta operand of Refract from any size in order to make it eventually cope with 16-bit floats. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Add a 64-bit implementation of OpIsInfNeil Roberts2018-04-171-3/+4
| | | | | | | | | | | | The only change neccessary is to change the type of the constant used to compare against. This has been tested against the arb_gpu_shader_fp64/execution/ fs-isinf-dvec tests using the ARB_gl_spirv branch. v2: Use nir_imm_floatN_t for the constant. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Use nir_imm_floatN_t for constants for GLSL450 builtinsNeil Roberts2018-04-171-1/+1
| | | | | | | | | | There is an existing macro that is used to choose between either a float or a double immediate constant based on the bit size of the first operand to the builtin. This is now changed to use the new nir_imm_floatN_t helper function to reduce the number of places that make this decision. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/builder: Add a nir_imm_floatN_t helperNeil Roberts2018-04-171-0/+13
| | | | | | | | This lets you easily build float immediates just given the bit size. If we have this single place here to handle this then it will be easier to add support for 16-bit floats later. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: return early when lowering a return at the end of a functionTimothy Arceri2018-04-171-0/+6
| | | | | | | Otherwise we create unused conditional return flags and things get unnecessarily ugly fast when lowering nested functions. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: merge the driver functions DrawBuffers and DrawBufferTimothy Arceri2018-04-175-16/+8
| | | | | | | The extra params we unused by the drivers that used DrawBuffers. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl: fix gcc 8 parenthesis warningMarc Dietrich2018-04-171-2/+2
| | | | | | | | | | | | | | | | | | | fixes warnings like this: [184/1137] Compiling C++ object 'src/compiler/glsl/glsl@sta/lower_jumps.cpp.o'. In file included from ../src/mesa/main/mtypes.h:48, from ../src/compiler/glsl_types.h:149, from ../src/compiler/glsl/lower_jumps.cpp:59: ../src/compiler/glsl/lower_jumps.cpp: In member function '{anonymous}::block_record {anonymous}::ir_lower_jumps_visitor::visit_block(exec_list*)': ../src/compiler/glsl/list.h:650:17: warning: unnecessary parentheses in declaration of 'node' [-Wparentheses] for (__type *(__inst) = (__type *)(__list)->head_sentinel.next; \ ^ ../src/compiler/glsl/lower_jumps.cpp:510:7: note: in expansion of macro 'foreach_in_list' foreach_in_list(ir_instruction, node, list) { ^~~~~~~~~~~~~~~ Signed-off-by: Marc Dietrich <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* compiler: int8/uint8 fixesRob Clark2018-04-161-25/+12
| | | | | | | | | | | | A couple spots were missed for handling of the new INT8/UINT8 base type. Also de-duplicate get_base_type().. get_scalar_type() had nearly the same switch statement, with the exception that anything with base_type that was not scalar would return error_type. So just handle that one special case in get_scalar_type(). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: don't emit partial flushes for internal CS flushes onlyMarek Olšák2018-04-1610-20/+32
| | | | | Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATEMarek Olšák2018-04-161-10/+26
| | | | | | | | There is a kernel patch that adds the new flag. Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement mechanism for IBs without partial flushes at the end (v6)Marek Olšák2018-04-163-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This patch doesn't enable the behavior. It will be enabled in a later commit.) Draw calls from multiple IBs can be executed in parallel. v2: do emit partial flushes on SI v3: invalidate all shader caches at the beginning of IBs v4: don't call si_emit_cache_flush in si_flush_gfx_cs if not needed, only do this for flushes invoked internally v5: empty IBs should wait for idle if the flush requires it v6: split the commit If we artificially limit the number of draw calls per IB to 5, we'll get a lot more IBs, leading to a lot more partial flushes. Let's see how the removal of partial flushes changes GPU utilization in that scenario: With partial flushes (time busy): CP: 99% SPI: 86% CB: 73: Without partial flushes (time busy): CP: 99% SPI: 93% CB: 81% Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nir: fix ir_binop_gequal glsl_to_nir conversionErico Nunes2018-04-161-1/+1
| | | | | | | | | | ir_binop_gequal needs to be converted to nir_op_sge when native integers are not supported in the driver. Otherwise it becomes no different than ir_binop_less after the conversion. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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