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* mesa: invalidate pipeline status after glUseProgramStagesTapani Pälli2015-12-101-0/+2
| | | | | | | | | | | | This will cause validation to run during next draw, this is done because possible changes in used stages and programs can cause invalid pipeline state. This fixes a subtest in following CTS test: ES31-CTS.sepshaderobjs.StateInteraction Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa/varray: set double arrays to non-normalised.Dave Airlie2015-12-101-1/+1
| | | | | | | | | | | Doesn't have any effect in practice I don't think, but CTS reads back using GetVertexAttrib. This fixes: GL41-CTS.vertex_attrib_64bit.get_vertex_attrib Cc: "11.0 11.1" <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* clover: Fix build against LLVM 3.8 SVN >= r255078Michel Dänzer2015-12-101-0/+4
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* mesa: fix ID usage for buffer warningsBrian Paul2015-12-091-6/+12
| | | | | | We need a different ID pointer for each call site. Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno: little clean up in fd_create_surfaceSerge Martin2015-12-091-15/+16
| | | | | | in order to avoid returing invalid adress if CALLOC_STRUCT return NULL. Signed-off-by: Rob Clark <[email protected]>
* freedreno: change to goto failSerge Martin2015-12-091-4/+2
| | | | | | in fd_resource_transfer_map, like the others error cases Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix bind_sampler_states when hwcso is NULLSerge Martin2015-12-093-0/+9
| | | | | | | | | | src/gallium/tests/trivial/compute.c expects samplers to be cleaned when the samplers list is NULL. Like in radeon, the function behave like when the number of samplers parameter is set to 0. [small s/hwsco/hwcso/ typo fix] Signed-off-by: Rob Clark <[email protected]>
* gallium/util: Make u_prims_for_vertices() safeEdward O'Callaghan2015-12-091-0/+3
| | | | | | | | | | | | | | | Let us avoid trapping in hardware from a SIGFPE and instead assert on a zero divisor. Hint: This can occur if a PIPE_PRIM_? is not handled in u_prim_vertex_count() that results in ' info ' not being initialized in the expected manner. Further, we also fix a possibly NULL pointer dereference from ' info ' being NULL from a u_prim_vertex_count() call. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nv50,nvc0: fix use-after-free when vertex buffers are unboundPatrick Rudolph2015-12-092-7/+6
| | | | | | | | | | | | Always reset the vertex bufctx to make sure there's no pointer to an already freed pipe_resource left after unbinding buffers. Fixes use after free crash in nvc0_bufctx_fence(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004 Signed-off-by: Patrick Rudolph <[email protected]> [imirkin: simplify nvc0 fix, apply to nv50] Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* mesa: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
| | | | | | | s/suports/supports/ Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glx: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
| | | | | | | s/suports/supports/ Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/osmesa: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
| | | | | | | s/suport/support/ Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* meta: Fix a typo in a print messageAndreas Boll2015-12-091-1/+1
| | | | | | | s/Unkown/Unknown/ Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Fix typos in print messagesAndreas Boll2015-12-092-2/+2
| | | | | | | | s/inconsistant/inconsistent/ s/occurences/occurrences/ Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
| | | | | | | s/suports/supports/ Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: initialize pipe_driver_query_info entries with a macroBrian Paul2015-12-091-15/+28
| | | | | | | To be safe, set all the fields in case the enums ordering/values ever change. Reviewed-by: Charmaine Lee <[email protected]>
* mesa: detect inefficient buffer use and report through debug outputBrian Paul2015-12-092-0/+59
| | | | | | | | | | | | | | | When a buffer is created with GL_STATIC_DRAW, its contents should not be changed frequently. But that's exactly what one application I'm debugging does. This patch adds code to try to detect inefficient buffer use in a couple places. The GL_ARB_debug_output mechanism is used to report the issue. NVIDIA's driver detects these sort of things too. Other types of inefficient buffer use could also be detected in the future. Reviewed-by: José Fonseca <[email protected]>
* i965: Resolve color and flush for all active shader images in ↵Francisco Jerez2015-12-091-0/+18
| | | | | | | | | | | | | | | | | intel_update_state(). Fixes arb_shader_image_load_store/execution/load-from-cleared-image.shader_test. Couldn't reproduce any significant FPS regression in CPU-bound benchmarks from the Finnish benchmarking system on neither VLV nor BSW after 30 runs with 95% confidence level. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92849 Cc: Chris Wilson <[email protected]> Cc: Jason Ekstrand <[email protected]> Cc: "11.0 11.1" <[email protected]> Tested-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Document inconsistent units the URB size is represented in.Francisco Jerez2015-12-092-1/+12
| | | | | | Every other gen the representation of the URB size was changed and previous ones weren't updated. I'd be willing to write a series normalizing this to be KB on all generations if anybody else cares.
* i965: Hook up L3 partitioning state atom.Francisco Jerez2015-12-092-2/+6
| | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Work around L3 state leaks during context switches.Francisco Jerez2015-12-094-5/+73
| | | | | | | | | | | | | | | | | | This is going to require some rather intrusive kernel changes to fix properly, in the meantime (and forever on at least pre-v4.1 kernels) we'll have to restore the hardware defaults at the end of every batch in which the L3 configuration was changed to avoid interfering with the DDX and GL clients that use an older non-L3-aware version of Mesa. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> v2: Optimize look-up of the default configuration by assuming it's the first entry of the L3 config array in order to avoid an FPS regression in GpuTest Triangle and SynMark OglBatch2-7 on most affected platforms. Reviewed-by: Jordan Justen <[email protected]>
* i965: Add debug flag to print out the new L3 state during transitions.Francisco Jerez2015-12-093-0/+19
| | | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Implement L3 state atom.Francisco Jerez2015-12-093-0/+88
| | | | | | | | | | | | | | The L3 state atom calculates the target L3 partition weights when the program bound to some shader stage is modified, and in case they are far enough from the current partitioning it makes sure that the L3 state is re-emitted. v2: Fix for inconsistent units the context URB size is expressed in. Clamp URB size to 1008 KB on SKL due to FF hardware limitation. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Calculate appropriate L3 partition weights for the current pipeline state.Francisco Jerez2015-12-092-0/+54
| | | | | | | | | | | | | | | | | | | | This calculates a rather conservative partitioning of the L3 cache based on the shaders currently bound to the pipeline and whether they use SLM, atomics, images or scratch space. The result is intended to be fine-tuned later on based on other pipeline state. Note that the L3 partitioning calculated for VLV in the non-SLM non-DC case differs from the hardware defaults in that it doesn't include a DC partition and has twice as much RO cache space -- This is an intentional functional change that improves performance in several bandwidth-bound benchmarks on VLV (5% significance): SynMark OglTexFilterAniso by 14.18%, SynMark OglTexFilterTri by 7.15%, Unigine Heaven by 4.91%, SynMark OglShMapPcf by 2.15%, GpuTest Fur by 1.83%, SynMark OglDrvRes by 1.80%, SynMark OglVsTangent by 1.71%, and a few other benchmarks from the Finnish system by less than 1%. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Implement selection of the closest L3 configuration based on a vector ↵Francisco Jerez2015-12-091-0/+95
| | | | | | | | | | | | of weights. The input of the L3 set-up code is a vector giving the approximate desired relative size of each partition. This implements logic to compare the input vector against the table of validated configurations for the device and pick the closest compatible one. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ↵Francisco Jerez2015-12-094-3/+9
| | | | | | | | readable. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/hsw: Enable L3 atomics.Francisco Jerez2015-12-091-0/+14
| | | | | | | | | | | | | | | | | | | Improves performance of the arb_shader_image_load_store-atomicity piglit test by over 25x (which isn't a real benchmark it's just heavy on atomics -- the improvement in a microbenchmark I wrote a while ago seemed to be even greater). The drawback is one needs to be extra-careful not to hang the GPU (in fact the whole system). A DC partition must have been allocated on L3, the "convert L3 cycle for DC to UC" bit may not be set, the MOCS L3 cacheability bit must be set for all surfaces accessed using DC atomics, and the SCRATCH1 and ROW_CHICKEN3 bits must be kept in sync. A fairly recent kernel is required for the command parser to allow writes to these registers. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Implement programming of the L3 configuration.Francisco Jerez2015-12-091-0/+95
| | | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Import tables enumerating the set of validated L3 configurations.Francisco Jerez2015-12-092-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | It should be possible to use additional L3 configurations other than the ones listed in the tables of validated allocations ("BSpec » 3D-Media-GPGPU Engine » L3 Cache and URB [IVB+] » L3 Cache and URB [*] » L3 Allocation and Programming"), but it seems sensible for now to hard-code the tables in order to stick to the hardware docs. Instead of setting up the arbitrary L3 partitioning given as input, the closest validated L3 configuration will be looked up in these tables and used to program the hardware. The included tables should work for Gen7-9. Note that the quantities are specified in ways rather than in KB, this is because the L3 control registers expect the value in ways, and because by doing that we can re-use a single table for all GT variants of the same generation (and in the case of IVB/HSW and CHV/SKL across different generations) which generally have different L3 way sizes but allow the same combinations of way allocations. v2: Use slice count from the devinfo structure instead of the gt number to implement get_l3_way_size(). Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add slice count to the brw_device_info structure.Francisco Jerez2015-12-092-0/+25
| | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.Francisco Jerez2015-12-091-1/+3
| | | | | | | | | According to the hardware docs a DC flush is sufficient to make CS_STALL happy, there's no need to add STALL_AT_SCOREBOARD whenever it's present. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Define state flag to signal that the URB size has been altered.Francisco Jerez2015-12-093-0/+6
| | | | | | | | This will make sure that we recalculate the URB layout anytime the URB size is modified by the L3 partitioning code. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Keep track of whether LRI is allowed in the context struct.Francisco Jerez2015-12-092-1/+8
| | | | | | | | | | | | This stores the result of can_do_pipelined_register_writes() in the context struct so we can find out later whether LRI can be used to program the L3 configuration. v2: * Split change of gen check in can_do_pipelined_register_writes (jljusten) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Adjust gen check in can_do_pipelined_register_writesFrancisco Jerez2015-12-091-2/+5
| | | | | | | | | | Allow for pipelined register writes for gen < 7. v2: * Split from another patch and adjust comment (jljusten) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Define symbolic constants for some useful L3 cache control registers.Francisco Jerez2015-12-091-0/+53
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* radeonsi: handle loading doubles as geometry shader inputs.Dave Airlie2015-12-091-4/+16
| | | | | | | | This adds the double code to the geometry shader input handling. Reviewed-by: Michel Dänzer <[email protected]> Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: handle doubles in lds load path.Dave Airlie2015-12-091-0/+8
| | | | | | | | This handles loading doubles from LDS properly. Reviewed-by: Michel Dänzer <[email protected]> Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: handle geometry dynamic input array indexDave Airlie2015-12-091-2/+11
| | | | | | | | | | | This fixes: glsl-1.50/execution/geometry/dynamic_input_array_index.shader_test my profanity. We need to load the AR register with the value from the index reg Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix geom shader input indirect indexing.Dave Airlie2015-12-091-2/+30
| | | | | | | | | | This fixes: gs-input-array-vec4-index-rd The others run out of gprs unfortunately. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix outputing to non-0 buffers for stream 0.Dave Airlie2015-12-091-2/+4
| | | | | | | | | | | | | This fixes: arb_transform_feedback3-ext_interleaved_two_bufs_gs arb_transform_feedback3-ext_interleaved_two_bufs_gs_max transform-feedback-builtins If we are only emitting one ring, then emit all output buffers on it. Cc: "11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: Add ARB_copy_image supportEdward O'Callaghan2015-12-091-1/+1
| | | | | | | | [airlied: update relnotes] Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: allow copying between compatible un/compressed formatsEdward O'Callaghan2015-12-091-1/+2
| | | | | | | | | | | | See: `commit e82c527f1fc2f8ddc64954ecd06b0de3cea92e93` which is where a block in src maps to a pixel in dst and vice versa. e.g. DXT1 <-> R32G32_UINT DXT5 <-> R32G32B32A32_UINT Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: fix cutoff for using r63 vs r127 when replacing zeroIlia Mirkin2015-12-081-1/+2
| | | | | | | | | | | The only effect here is a space savings - 822 programs in shader-db affected with the following overall change: total bytes used in shared programs : 44154976 -> 44139880 (-0.03%) Fixes: 641eda0c (nv50/ir: r63 is only 0 if we are using less than 63 registers) Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: prefer to color mad def and src2 with the same colorIlia Mirkin2015-12-081-0/+14
| | | | | | | | | | | | | | | | This allows us to use the short encoding, and potentially fold immediates in later on. total instructions in shared programs : 6379731 -> 6367861 (-0.19%) total gprs used in shared programs : 728502 -> 728683 (0.02%) total local used in shared programs : 9904 -> 9904 (0.00%) total bytes used in shared programs : 44661008 -> 44154976 (-1.13%) local gpr inst bytes helped 0 51 7267 20306 hurt 0 232 125 274 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: reduce degree limit on ops that can't encode large reg destsIlia Mirkin2015-12-081-3/+34
| | | | | | | Operations that take immediates can only encode registers up to 64. This fixes a shader in a "Powered by Unity" intro. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: only unspill once ahead of a group of instructionsIlia Mirkin2015-12-081-5/+20
| | | | | | | | | | | | | | | | | | | | | | | We already semi-did this but the list of uses as unsorted, so it was unreliable. Sort the uses by bb and serial, and don't unspill for each instruction in a sequence. (And also don't unspill multiple times for a single instruction that uses the value in question multiple times.) This causes a minor reduction in generated instructions for shader-db (as few programs spill) but more importantly it brings determinism to each run's output. On SM10: total instructions in shared programs : 6387945 -> 6379359 (-0.13%) total gprs used in shared programs : 728544 -> 728544 (0.00%) total local used in shared programs : 9904 -> 9904 (0.00%) local gpr inst bytes helped 0 0 322 322 hurt 0 0 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: check if the target supports the new offset before inliningIlia Mirkin2015-12-084-3/+25
| | | | | | Fixes: abd326e81b (nv50/ir: propagate indirect loads into instructions) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93300 Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: fix fp64 inputs to geom shader.Dave Airlie2015-12-091-4/+12
| | | | | | | | | | | This fixes the fetching of fp64 inputs to the geometry shader, this fixes the recently posted piglit's arb_gpu_shader_fp64/execution/gs-fs-vs-double-array.shader_test arb_vertex_attrib_64bit/execution/gs-fs-vs-attrib-double-array.shader_test Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir: Optimize useless comparisons against true/false.Matt Turner2015-12-081-2/+4
| | | | | | | | | | Reviewed-by: Jason Ekstrand <[email protected]> [v1] Reviewed-by: Eric Anholt <[email protected]> [v1] v2: Move new rule to Boolean simplification section Add a a@bool != true simplification Suggested-by: Neil Roberts <[email protected]>
* glsl: Switch opcode and avail parameters to binop().Matt Turner2015-12-081-17/+18
| | | | | | To make it match unop(). Reviewed-by: Ian Romanick <[email protected]>
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