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* i965: Implement interface to edit binding table entriesAbdiel Janulgue2015-07-182-0/+64
| | | | | | | | | | | | | | | | Unlike normal software binding tables where the driver has to manually generate and fill a binding table array which are then uploaded to the hardware, the resource streamer instead presents the driver with an option to fill out slots for individual binding table indices. The hardware accumulates the state for these combined edits which it then automatically flushes to a binding table pool when the binding table pointer state command is invoked. v2: Clarify binding table edit bit aligment (Topi). v3: Make comments and function names more clearer (Ken). Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-188-4/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the binding table enable command which is also used to allocate a binding table pool where where hardware-generated binding table entries are flushed into. Each binding table offset in the binding table pool is unique per each shader stage that are enabled within a batch. Also insert the required brw_tracked_state objects to enable hw-generated binding tables in normal render path. v2: - Use MOCS in binding table pool alloc for GEN8 - Fix spurious offset when allocating binding table pool entry and start from zero instead. v3: - Include GEN8 fix for spurious offset above. v4: - Fixup wrong packet length in enable/disable hw-binding table for GEN8 (Ville). - Don't invoke HW-binding table disable command when we dont have resource streamer (Chris). v5: - Reorder the state cache invalidate flush so it happens in-between enabling hw-generated binding tables and the previous sw-binding table GPU state (Chris). v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables(). - Adhere to coding guidelines and make comments more informative. Cc: [email protected] Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-187-2/+36
| | | | | | | | | | | | | | | | | | | | | Check first if the hardware and kernel supports resource streamer. If this is allowed, tell the kernel to enable the resource streamer enable bit on MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER execbuffer flags. v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel supports RS (Ken). - Add brw_device_info::has_resource_streamer and toggle it for Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken). v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel. v4: - Always inspect the getparam.value (Chris Wilson). v5: - Fold redundant devinfo->has_resource_streamer check in context create into init screen. Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-182-0/+33
| | | | | | | | | | | v2: Use macros for HW binding table edits (Topi) v3: Add Broadwell support. v4: Make hardware binding table bit definitions even more clearer (Ken) Cc: [email protected] Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* vc4: Switch to using a separate ioctl for making shaders.Eric Anholt2015-07-174-12/+78
| | | | | | | | | This gives the kernel a chance to validate and lock down the data, without having to deal with mmap zapping. With this, GLBenchmark stops on a texture relocations, because we'd recycled a shader BO as another shader and failed to revalidate, since we weren't clearing the cached validation state on mmap faults.
* mesa: fix up some texture error checksRoland Scheidegger2015-07-182-21/+21
| | | | | | | | | | | In particular, we were incorrectly accepting s3tc (and lots of others) for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d targets. At this time, the only allowed formats for these calls are the bptc ones, since none of the specific extensions allow it (astc hdr would). Also, fix up a bug in _mesa_target_can_be_compressed - 3d target needs to be allowed for bptc formats. Reviewed-by: Brian Paul <[email protected]>
* vc4: Fix printing of shader-db debug when shader-db isn't turned on.Eric Anholt2015-07-171-4/+6
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* vc4: Add debugging on texture relocation validation failures.Eric Anholt2015-07-171-7/+13
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* vc4: Also consider uniform 0 in uniform lowering.Eric Anholt2015-07-171-3/+3
| | | | The hash table considers key 0 to be the empty key.
* vc4: Use the pure/const attributes on a bunch of our QPU functions.Eric Anholt2015-07-172-18/+18
| | | | | | On a release build, this makes the rest of vc4_qpu_validate.c go away (the compiler didn't know that our qpu helper function calls had no side effects).
* mesa: Detect and provide macros for function attributes pure and const.Eric Anholt2015-07-171-0/+20
| | | | | | | | | | | | | These are really useful hints to the compiler in the absence of link-time optimization, and I'm going to use them in VC4. I've made the const attribute be ATTRIBUTE_CONST unlike other function attributes, because we have other things in the tree #defining CONST for their own unrelated purposes. v2: Alphabetize. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965/fs: don't make unused payload registers interfereConnor Abbott2015-07-171-1/+6
| | | | | | | | | | | | | | | | | Before, we were setting payload_last_use_ip for unused payload registers to 0, which made them interfere with whatever the first instruction wrote to due to the workaround for SIMD16 uniform arguments. Just use -1 to mean "unused" instead, and then skip setting any interferences for unused payload registers. instructions in affected programs: 0 -> 0 helped: 0 HURT: 0 GAINED: 1 LOST: 0 Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965/fs: remove special case in setup_payload_interference()Connor Abbott2015-07-171-20/+0
| | | | | | | | | | | | | | | | | | regs_read() will handle LINTERP for us since the previous commit. In addition, we were being too conservative, since it will only read 2 registers on SIMD8. instructions in affected programs: 9061 -> 8893 (-1.85%) helped: 10 HURT: 0 GAINED: 0 LOST: 0 All of the changes were due to spills being eliminated, mostly in KSP shaders. Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965/fs: Mark last used ip for all regs read in the payloadJordan Justen2015-07-171-1/+4
| | | | | | | | | | | | | | | | | | | If a source register in the push constant registers uses more than one register, then we wouldn't update payload_last_use_ip for subsequent registers. Unlike most uniform data pushed into registers, the CS gl_LocalInvocationID data varies per execution channel. Therefore for SIMD16 mode, we have vec16 data in the payload. In this case we then need to mark 2 registers in payload_last_use_ip as last used by the instruction. There's a similar situation for the z and w coordinates of gl_FragCoord for fragment shaders, where it had only happened to work before because of some bogus interferences which the next commit removes. (Connor: added bit about gl_FragCoord to commit message) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965/fs: fix regs_read() for LINTERPConnor Abbott2015-07-171-1/+2
| | | | | | | | The second source always stays within the same SIMD8 register. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* nir: add nir_foreach_instr_safe_reverse()Connor Abbott2015-07-171-0/+2
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* nir: add nir_instr_is_first() and nir_instr_is_last() helpersConnor Abbott2015-07-171-0/+12
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965/cs: Use dispatch width of 8 for cs terminate payload setupJordan Justen2015-07-161-1/+1
| | | | | | | | This prevents an assertion failure in brw_fs_live_variables.cpp, fs_live_variables::setup_one_write: Assertion `var < num_vars' failed. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATEJordan Justen2015-07-161-0/+3
| | | | | | | | This prevents an assertion failure in brw_fs_live_variables.cpp, fs_live_variables::setup_one_read: Assertion `var < num_vars' failed. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* program: Allow redundant OPTION ARB_fog_* directives.Kenneth Graunke2015-07-161-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A fragment program from "Pixel Piracy" contains redundant OPTION directives: !!ARBfp1.0 OPTION ARB_precision_hint_fastest; OPTION ARB_fog_exp2; OPTION ARB_precision_hint_fastest; OPTION ARB_fog_exp2; ... We already allow redundant ARB_precision_hint_fastest directives, but disallow the redundant (yet consistent) ARB_fog_exp2 directives, failing to compile the program. The specification seems to contradict itself - the main text says that only one fog application option may be specified, but then backpedals, indicating the intent is to disallow /contradictory/ flags. One of the issues suggests that specifying contradictory ones is stupid, but allowed, and only the last one should take effect. Accepting multiple redundant (but consistent) directives seems harmless, and like a reasonable interpretation of the specification. It also fixes a fragment program found in the wild. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad v4: Use parens to get the order right from v3. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-167-51/+47
| | | | This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]> (v2) Reviewed-by: Anuj Phogat <[email protected]> (v2) Reviewed-by: Chad Versace <[email protected]> (v2)
* i965/fs: Factor out universally broken calculation of the register component ↵Francisco Jerez2015-07-164-12/+23
| | | | | | | | | | | | | | size. This in principle simple calculation was being open-coded in a number of places (in a series I haven't yet sent for review there will be a couple more), all of them were subtly broken in one way or another: None of them were handling the HW_REG case correctly as pointed out by Connor, and fs_inst::regs_read() was handling the stride=0 case rather naively. This patch solves both problems and factors out the calculation as a new fs_reg method. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.Francisco Jerez2015-07-163-35/+12
| | | | | | | | | | | | | | | | | | This gets rid of two no16() fall-backs and should allow better scheduling of the generated IR. There are no uses of usubBorrow() or uaddCarry() in shader-db so no changes are expected. However the "arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow" and "arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry" piglit tests go from 40 to 28 instructions. The reason is that the plain ADD instruction can easily be CSE'ed with the original addition, and the b2i negation can easily be propagated into the source modifier of another instruction, so effectively both operations are performed with just one instruction. v2: Rely on carry_to_arith() and borrow_to_arith() to lower these (Ilia Mirkin). Reviewed-by: Matt Turner <[email protected]>
* i965: Implement b2f and b2i using negation.Francisco Jerez2015-07-162-9/+2
| | | | | | | | | | | | | | | | | Booleans are represented as 0/-1 on modern hardware which means we can just negate them to convert them into a numeric type. Negation has the benefit that it can be implemented using a source modifier which can easily be propagated into some other instruction. shader-db results on HSW: total instructions in shared programs: 6349082 -> 6346693 (-0.04%) instructions in affected programs: 40948 -> 38559 (-5.83%) helped: 123 HURT: 1 GAINED: 1 LOST: 0 Reviewed-by: Matt Turner <[email protected]>
* gallium: add interface for writable shader buffersMarek Olšák2015-07-162-0/+28
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add interface for writable shader imagesMarek Olšák2015-07-1610-27/+120
| | | | | | PIPE_CAPs will be added some other time. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add new limits for shader buffers and imagesMarek Olšák2015-07-163-4/+5
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add BIND flags for R/W buffers and imagesMarek Olšák2015-07-167-13/+19
| | | | | | | | | | | | | | | | | PIPE_CAPs and TGSI support will be added later. The TGSI support should be straightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE and TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary. The idea is: * ARB_shader_image_load_store should use set_shader_images. * ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1) if M shader storage buffers are supported. * ARB_shader_atomic_counters should use set_shader_buffers(slots M..N) if N-M+1 atomic counter buffers are supported. PIPE_CAPs can describe various constraints for early DX11 hardware. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGSMarek Olšák2015-07-1615-0/+18
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-162-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on hardware defaults the i915 kernel driver is going program custom MOCS tables system-wide on Gen9 hardware. The "WT" entry previously used for renderbuffers had a number of problems: It disabled caching on eLLC, it used a reserved L3 cacheability setting, and it used to override the PTE controls making renderbuffers always WT on LLC regardless of the kernel's setting. Instead use an entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE, L3CC=WB. The "WB" entry previously used for anything other than renderbuffers has moved to a different index in the new MOCS tables but it should have the same caching semantics as the old entry. Even though the corresponding kernel change ("drm/i915: Added Programming of the MOCS") is in a way an ABI break it doesn't seem necessary to check that the kernel is recent enough because the change should only affect Gen9 which is still unreleased hardware. v2: Update MOCS values for the new Android-incompatible tables introduced in v7 of the kernel patch. Cc: 10.6 <[email protected]> Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html Reviewed-by: Ben Widawsky <[email protected]>
* clover: little OpenCL status code logging cleanEdB2015-07-165-25/+32
| | | | | | | | s/build_error/compile_error in order to match the stored OpenCL status code. Make program::build catch and log every OpenCL error. Make tgsi error triggering uniform with the llvm one. Reviewed-by: Francisco Jerez <[email protected]>
* glsl: avoid compiler's segfault when processing operators with void argumentsRenaud Gaubert2015-07-162-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done by returning an rvalue of type void in the ast_function_expression::hir function instead of a void expression. This produces (in the case of the ternary) an hir with a call to the void returning function and an assignment of a void variable which will be optimized out (the assignment) during the optimization pass. This fix results in having a valid subexpression in the many different cases where the subexpressions are functions whose return values are void. Thus preventing to dereference NULL in the following cases: * binary operator * unary operators * ternary operator * comparison operators (except equal and nequal operator) Equal and nequal had to be handled as a special case because instead of segfaulting on a forbidden syntax it was now accepting expressions with a void return value on either (or both) side of the expression. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252 Signed-off-by: Renaud Gaubert <[email protected]> Reviewed-by: Gabriel Laskar <[email protected]> Reviewed-by: Samuel Iglesias Gonsalvez <[email protected]>
* r200: fix some potential big endian issuesRoland Scheidegger2015-07-165-129/+140
| | | | | | | | | | | | The formats chosen (both by texture format choser, fbo storage allocation) are different for big endian not just for rgba8 but also lower bit width formats (why I don't actually know). Even the function to test for renderable formats used different formats, however the actual colorbuffer setup did not. And the blitter did not take that into account neither. Untested (what could possibly go wrong...). Same as for r100. Acked-by: Marek Olšák <[email protected]>
* radeon: fix some potential big endian issuesRoland Scheidegger2015-07-164-90/+76
| | | | | | | | | | | The formats chosen (both by texture format choser, fbo storage allocation) are different for big endian not just for rgba8 but also lower bit width formats (why I don't actually know). Even the function to test for renderable formats used different formats, however the actual colorbuffer setup did not. And the blitter did not take that into account neither. Untested (what could possibly go wrong...). Acked-by: Marek Olšák <[email protected]>
* radeon/r200: mark state atoms as dirty after blitsRoland Scheidegger2015-07-162-0/+24
| | | | | | | | | | | Blit submits lots of packets which are usually handled by state atoms, so these must be dirtied. Not sure if this fixes anything, but it was a concern raised by bug 51658 (with this all issues there seen as actual bugs should be fixed, with the exception of the patch to upload non-used texenv state atoms which I just don't understand). Acked-by: Marek Olšák <[email protected]>
* r200: fix fbo rendering by disabling optimized texture format chooserRoland Scheidegger2015-07-161-1/+13
| | | | | | | | | | | | It is rather unfortunate that we don't know if a texture is going to be used as a rt later, and we lack the means to do something about a format chosen which we can't render to directly, so disable this and always chose renderable format for rgba8 textures. This addresses an issue raised on (old) bug, https://bugs.freedesktop.org/show_bug.cgi?id=51658 with gnome-shell, don't know if that's still applicable but it might fix other things as well. Acked-by: Marek Olšák <[email protected]>
* i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()Anuj Phogat2015-07-151-3/+3
| | | | | | | | | | | | | | | Along with fixing the type of pitch parameter, patch also changes the types of few local variables and function return type. Warnings fixed are: intel_mipmap_tree.c:671:7: warning: passing argument 3 of 'intel_get_yf_ys_bo_size' from incompatible pointer type intel_mipmap_tree.c:563:1: note: expected 'uint64_t *' but argument is of type 'long unsigned int *' Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Optimize batchbuffer macros.Matt Turner2015-07-156-42/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously OUT_BATCH was just a macro around an inline function which does brw->batch.map[brw->batch.used++] = dword; When making consecutive calls to intel_batchbuffer_emit_dword() the compiler isn't able to recognize that we're writing consecutive memory locations or that it doesn't need to write batch.used back to memory each time. We can avoid both of these problems by making a local pointer to the next location in the batch in BEGIN_BATCH(). Cuts 18k from the .text size. text data bss dec hex filename 4946956 195152 26192 5168300 4edcac i965_dri.so before 4928956 195152 26192 5150300 4e965c i965_dri.so after This series (including commit c0433948) improves performance of Synmark OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge. Reviewed-by: Chris Wilson <[email protected]>
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-156-22/+25
| | | | | | | The next patch will replace the .used field with an on-demand calculation of batchbuffer usage. Reviewed-by: Chris Wilson <[email protected]>
* i965: Split batch emission from relocation functions.Matt Turner2015-07-152-34/+30
| | | | | | | So that everything writing to the batch between BEGIN_BATCH() and ADVANCE_BATCH() goes through OUT_BATCH. Reviewed-by: Chris Wilson <[email protected]>
* i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().Matt Turner2015-07-151-2/+2
| | | | | | | | | | BEGIN_BATCH() and ADVANCE_BATCH() will contain "do {" and "} while (0)" respectively to allow declaring local variables used by intervening OUT_BATCH macros. As such, BEGIN_BATCH() and ADVANCE_BATCH() need to be in the same control flow. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* osmesa: fix OSMesaPixelsStore typoBrian Paul2015-07-152-2/+2
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91337 Cc: 10.6 <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* vc4: Cache the texture p1 for the sampler.Eric Anholt2015-07-143-49/+69
| | | | | Cuts another 12% of vc4_uniforms.o, in exchange for computing it at CSO creation time.
* vc4: Cache texture p0/p1 setup for the sampler view.Eric Anholt2015-07-143-28/+43
| | | | | In exchange for a bit of space and computation in CSO setup, we cut vc4_uniform.c (draw time) code size by 4.8%.
* vc4: Move uniforms handling to a separate file.Eric Anholt2015-07-143-314/+341
| | | | | The rest of vc4_program.c is about compiling, while this is about uniform emit at draw time.
* vc4: Fix some -Wdouble-promotion warnings.Eric Anholt2015-07-143-6/+6
| | | | | No code generation changes from this, but it'll be useful to have this next time I go checking -Wdouble-promotion.
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-142-0/+25
| | | | | | | | | | | | | | | | This field should always be set for gen8. In the bdw PRM, Volume 2d: Command Reference: Structures under INTERFACE_DESCRIPTOR_DATA, DWORD 6, Bits 9:0, Number of Threads in GPGPU Thread Group: "This field should not be set to 0 even if the barrier is disabled, since an accurate value is needed for proper pre-emption." In the HSW PRM, the it doesn't mention that it must always be set, but it should not hurt. Reported-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* vc4: Fix compiler warnings on release builds.Eric Anholt2015-07-144-7/+14
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