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* turnip: set VFD_INDEX_OFFSET in 3D clear/blit pathJonathan Marek2020-06-171-4/+8
| | | | | | | | This was missing an causing flakes when used after a test that set it to a non-zero value. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5509>
* spirv: do not set num_components for non-vectorized mbcnt_amd intrinsicSamuel Pitoiset2020-06-171-1/+2
| | | | | | | Fixes: 167fa2887f0 ("nir/validate: validate intr->num_components") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5493>
* st_glsl_to_nir: fix potential use after freeTimothy Arceri2020-06-171-2/+14
| | | | | | | | | | | | | | | When updating the shader info used by GL for the API we must remember to make sure to restore the pointers to its own name and label strings. There are a number of ways in which the nir copy of these strings can be freed before GL is finished with them. Fixes: 36be8c2fcf94 ("st/glsl_to_nir: use nir_shader_gather_info()") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2875 Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5488>
* glsl: small optimisation fix for uniform array resizingTimothy Arceri2020-06-171-15/+10
| | | | | | | | | The fix in the previous patch removed an erronous attempt to skip resizing variable types in each stage. Now that has been removed iterating over each shader stage is no longer required here. Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5487>
* glsl: fix uniform array resizing in the nir linkerTimothy Arceri2020-06-171-44/+42
| | | | | | | | | | | | | | | | | | | | | | The initial support tried to match uniform variables from different shaders based on the variables pointer. This will obviously never work, instead here we use the variables name whcih also means we must disable this optimisation for spirv. Using the base variable name works because when collecting uniform references we never iterate past the first array dimension, and only support resizing 1D arrays (we also don't support resizing arrays inside structs). We also drop the resized bool as we can't skip processing the var just because is was resized in another shader, we must resize the var in all shaders. Fixes: a34cc97ca3e1 ("glsl: when NIR linker enable use it to resize uniform arrays") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3130 Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5487>
* anv: enable VK_EXT_pipeline_creation_cache_controlIván Briano2020-06-172-0/+8
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
* anv: implement VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXTIván Briano2020-06-172-14/+41
| | | | | | | | | | | | | | | | v2: * Set pPipeline to NULL in the corresponding graphics/compute_create_pipeline function. * Keep current ANV behavior of bailing on the first real error. v3: * Don't return early if the pipeline succeeded. v:4(5?): * Simplify return conditions. Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
* anv: support externally synchronized pipeline cachesIván Briano2020-06-172-13/+32
| | | | | | | | Implement the VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT bits of the VK_EXT_pipeline_creation_cache_control extension. Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
* intel/compiler: Remove unnecessary optimization for MULSagar Ghuge2020-06-161-8/+0
| | | | | | | | | | | | 2 source instruction only support immediate for src1 operand, so no point in adding optimization condition for src0 oprand. v2: - Update commit message and don't remove ADD optimization (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5341>
* intel/compiler: Optimize integer add with 0 into movSagar Ghuge2020-06-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kaby Lake total instructions in shared programs: 326560 -> 323616 (-0.90%) instructions in affected programs: 178062 -> 175118 (-1.65%) helped: 129 HURT: 0 helped stats (abs) min: 1 max: 118 x̄: 22.82 x̃: 8 helped stats (rel) min: 0.35% max: 6.56% x̄: 2.57% x̃: 2.47% 95% mean confidence interval for instructions value: -27.71 -17.93 95% mean confidence interval for instructions %-change: -2.81% -2.32% Instructions are helped. total cycles in shared programs: 43741127 -> 45397851 (3.79%) cycles in affected programs: 40880261 -> 42536985 (4.05%) helped: 94 HURT: 34 helped stats (abs) min: 5 max: 6160 x̄: 598.91 x̃: 45 helped stats (rel) min: 0.20% max: 34.86% x̄: 2.52% x̃: 1.09% HURT stats (abs) min: 1 max: 76198 x̄: 50383.00 x̃: 69677 HURT stats (rel) min: 0.07% max: 48.41% x̄: 15.65% x̃: 6.49% 95% mean confidence interval for cycles value: 8023.10 17863.21 95% mean confidence interval for cycles %-change: <.01% 4.60% Cycles are HURT. total spills in shared programs: 1086 -> 978 (-9.94%) spills in affected programs: 897 -> 789 (-12.04%) helped: 24 HURT: 0 total fills in shared programs: 1686 -> 1584 (-6.05%) fills in affected programs: 1371 -> 1269 (-7.44%) helped: 24 HURT: 0 v2: - Use brw_reg_type_is_integer (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5341>
* util: enable futex usage on BSDs after 7dc2f4788288Jan Beich2020-06-163-2/+7
| | | | | | Reviewed-by: Eric Engestrom <[email protected]> Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5460>
* freedreno/ir3: add post-scheduler cp passRob Clark2020-06-165-0/+223
| | | | | | | | | | A pass to eliminate extra mov's from an array. We need to do this after scheduling so we know that there are not any potentially conflicting array writes between the original `mov` and it's use(s). Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2124 Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/cp: extract valid_flagsRob Clark2020-06-163-174/+178
| | | | | | | We'll also need this in the postsched-cp pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3: delay test support for vectorish instructionsRob Clark2020-06-162-5/+68
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3: add helpers to move instructionsRob Clark2020-06-164-6/+25
| | | | | | | | | A bit cleaner than open coding the list manipulation. Plus I want to use it in the next patch, rather than adding more open coded list futzing. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/delay: calculate delay properly for (rptN)'d instructionsRob Clark2020-06-161-1/+23
| | | | | | | | | When a sequence of same instruction is encoded with repeat flag, destination registers are written on successive cycles. Teach the delay calculation about this. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3: add test for delay slot calculationRob Clark2020-06-162-0/+178
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/print: print (r) flagRob Clark2020-06-161-0/+3
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/legalize: don't allow (nopN) if (rptN)Rob Clark2020-06-161-1/+2
| | | | | | | | | These two encodings are mutually exclusive. If the instruction is a vector(ish) `(rptN)` instruction, then we can't fold a `(nopN)` post- delay into it. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/a6xx: emit shader names in debug buildsRob Clark2020-06-161-0/+7
| | | | | | | To simplify mapping a shader in a cmdstream trace back to glsl. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno: splitup emit_string_markerRob Clark2020-06-162-21/+48
| | | | | | | | So that we can use it internally to emit string markers into a specified rb. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/cp: properly handle already-folded RELATIVRob Clark2020-06-161-3/+5
| | | | | | | | | | | | | | | In the `try_swap_mad_two_srcs()` case, valid_flags() gets called both for the src that we want to try to fold, and for the other src that we are trying to swap to make that possible. It can happen in the 2nd case that a RELATIV src has already been folded. Since `ssa()` returns non- null in both the `IR3_REG_SSA` and `IR3_REG_ARRAY` cases (in the later case, it is the dependent array access that the current instruction cannot be moved ahead of), we need to explicitly check that the src reg we are looking at is still an SSA src. Reported-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/ir3/validate: also check instr->addressRob Clark2020-06-161-0/+9
| | | | | | | | Verify that instructions which have a relative src and/or dest, have `instr->address`. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/sched: reset delay counters at start of blockRob Clark2020-06-162-0/+4
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* freedreno/log-parser: fix compute timesRob Clark2020-06-161-0/+1
| | | | | | | | | We also need to clear the table of compute times at the end of the frame, otherwise results shown will include all the compute jobs since the beginning of the trace. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
* anv: add an option to disable secondary command buffer callsLionel Landwerlin2020-06-164-2/+10
| | | | | | | | | | | | | Those are currently hurting Felix' ability to look at the batches. We can probably detect this in the aubinator but that's a bit more work than falling back to the previous behavior. v2: Condition VK_KHR_performance_query to not using this variable (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5391>
* nir/intrinsics: Put the _intel intrinsics together at the endJason Ekstrand2020-06-161-12/+12
| | | | | | | | | All the other driver-specific intrinsics are at the end of the file so Intel's should go there too. Reviewed-by: Sagar Ghuge<[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5503>
* softpipe: change vendor name to something more generic.Dave Airlie2020-06-171-1/+1
| | | | | | | | | For consistency with the llvmpipe driver. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed by: Jose Fonseca <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5483>
* llvmpipe: change vendor to be more generic.Dave Airlie2020-06-171-1/+1
| | | | | | | | | | If submitting for conformance it is probably better to have a generic name for vendor here. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed by: Jose Fonseca <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5483>
* virgl: change vendor id to reflect reality more.Dave Airlie2020-06-171-1/+1
| | | | | | | | | | | virgl vendor id should probably be little more generic now. I think I picked this becuase the virtio pci id space was under RH's name and they did pay for it, but at this point I think it's better to just use something generic. Reviewed-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5483>
* anv: Add anv_pipeline_init/finish helpersJason Ekstrand2020-06-163-56/+84
| | | | | | | | This cleans up pipline create/destroy a bit after the compute/gfx split. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5457>
* anv: Add an anv_batch_set_storage helperJason Ekstrand2020-06-164-7/+15
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5457>
* anv,iris: unbreak on BSDs after 812cf5f522ab,abf8aed68047Jan Beich2020-06-162-3/+2
| | | | | | | | | | | | ../src/intel/vulkan/anv_gem.c:31:10: fatal error: 'linux/sync_file.h' file not found #include <linux/sync_file.h> ^~~~~~~~~~~~~~~~~~~ ../src/gallium/drivers/iris/iris_fence.c:29:10: fatal error: 'linux/sync_file.h' file not found #include <linux/sync_file.h> ^~~~~~~~~~~~~~~~~~~ Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5463>
* aco: don't allow SGPRs on logical phisDaniel Schürmann2020-06-161-1/+1
| | | | | | | aco_validate() is called after phi lowering, now. Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5496>
* aco: reorder calls to aco_validate() and cleanup aco_compile_shader()Daniel Schürmann2020-06-161-15/+7
| | | | | | | | The first call of aco_validate should happen after phi lowering. Otherwise, subdword restrictions might be violated Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5496>
* panfrost: Implement ARB_depth_clampIcecream952020-06-164-3/+23
| | | | | | | This significantly improves the quality of shadows in OpenMW. Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5453>
* panfrost: Clean up panfrost_frag_meta_rasterizer_updateIcecream952020-06-161-7/+7
| | | | | | | | Create a pointer to ctx->rasterizer->base so it isn't repeatedly referred to. Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5453>
* iris: Fix documentation for _iris_batch_flushRohan Garg2020-06-161-6/+0
| | | | | | | | _iris_batch_flush has no in_fence and out_fence parameters Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5470>
* zink: expose GLSL 1.30Erik Faye-Lund2020-06-161-1/+1
| | | | | Reviewed-By: Mike Blumenkrantz <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5479>
* zink: enable cull-distance if supportedErik Faye-Lund2020-06-161-2/+0
| | | | | | | | This is already implemented, and we just need to flip the switch to turn it on. Reviewed-By: Mike Blumenkrantz <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5479>
* gallium/hud: don't use user vertex buffersErik Faye-Lund2020-06-161-2/+5
| | | | | | | | This gains back some performance lost in the previous commit, by bypassing u_vbuf. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5417>
* Revert "gallium/hud: don't use user vertex buffers"Erik Faye-Lund2020-06-162-22/+8
| | | | | | | | | | | | | | | | | | The approach taken in this commit only works on drivers that expose the PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT capability. For drivers that don't, the buffer has been unmapped by the time we get to hud_draw_colored_prims, leading to crashes. It's not easy to fix the code, but drivers that do support coherent mapping will most likely do the right think themseleves, so let's just go back to using user-buffers here. This reverts commit 4fe1fd4df40ac91b2783e3604fd81e6a6faf0cd2. Fixes: 4fe1fd4df40 ("gallium/hud: don't use user vertex buffers") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3106 Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5417>
* nir/validate: validate intr->num_componentsRob Clark2020-06-161-0/+18
| | | | | | | | | | Validate that num_components is only set for vectorized instructions, to prevent other nir passes or driver backends from mistakenly relying on num_components for non-vectorized instructions. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* vc4: don't relay on intr->num_components for non-vectorized intrinsicsJose Maria Casanova Crespo2020-06-161-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* v3d: don't use intr->num_components for non-vectorized intrinsicsRob Clark2020-06-162-2/+1
| | | | | | Squashed-in-fix-from: Jose Maria Casanova Crespo <[email protected]> Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* spriv: don't set num_components for non-vectorised intrinsicsRob Clark2020-06-162-5/+5
| | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* nir/lower-atomics-to-ssbo: don't set num_componentsRob Clark2020-06-161-7/+8
| | | | | | | | | Of the possible intrinsics generated, only load_ssbo is vectorized (and store_ssbo is never generated) Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* nir/builder: don't set intr->num_componentsRob Clark2020-06-161-1/+0
| | | | | | | | The "load-sysval" intrinsics are not vectorized. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* radv: don't set num_components for non-vectorized intrinsicsRob Clark2020-06-161-1/+0
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
* freedreno/ir3: don't rely on intr->num_componentsRob Clark2020-06-164-22/+20
| | | | | | | | | | | | It is better to use `nir_intrinsic_dest_components()` which also handles the case of intrinsics with a fixed number of dest components. Somehow this starts showing up with a nir_serialize round-trip with shader-cache. But we really shouldn't have been relying on `intr->num_components` directly. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5371>
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