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* i965/clear: Quantize the depth clear value based on the formatJason Ekstrand2017-08-211-2/+12
| | | | | | | | | | | | | | | | | | In f9fd976e8adba733b08d we changed the clear value to be stored as an isl_color_value. This had the side-effect same clear value check is now happening directly between the f32[0] field of the isl_color_value and ctx->Depth.Clear. This isn't what we want for two reasons. One is that the comparison happens in floating point even for Z16 and Z24 formats. Worse than that, ctx->Depth.Clear is a double so, even for 32-bit float formats, we were comparing as doubles and not floats. This means that the test basically always fails for anything other than 0.0f and 1.0f. This caused a slight performance regression in Lightsmark 2008 because it was using a depth clear value of 0.999 which can't be stored in a 32-bit float so we were doing unneeded resolves. Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/101678 Cc: "17.2" <[email protected]>
* mesa/st: simplify some UBO index logicTimothy Arceri2017-08-221-3/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965: enable STD430 packing by default on IVB+Timothy Arceri2017-08-221-0/+16
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: pass UseSTD430AsDefaultPacking to where it will be usedTimothy Arceri2017-08-229-44/+94
| | | | | | | Here we also make use of the UseSTD430AsDefaultPacking constant and call the new get_internal_ifc_packing() helper. Reviewed-by: Marek Olšák <[email protected]>
* glsl: add get_internal_ifc_packing() type helperTimothy Arceri2017-08-221-0/+21
| | | | | | | This is used to avoid code duplication when selecting the packing type for shared and packed layouts. Reviewed-by: Marek Olšák <[email protected]>
* mesa: add UseSTD430AsDefaultPacking constantTimothy Arceri2017-08-221-0/+9
| | | | | | | This will be used to enable the STD430 layout as the default for UBOs and SSBOs with layouts of shared/packed rather than STD140. Reviewed-by: Marek Olšák <[email protected]>
* clover/device: Calculate CL_DEVICE_MEM_BASE_ADDR_ALIGN in deviceAaron Watry2017-08-213-1/+9
| | | | | | | | | | | | | | | | | | | | | | The CL CTS queries CL_DEVICE_MEM_BASE_ADDR_ALIGN for a device and then allocates user pointers aligned to that value for its tests. The minimum value is defined as: the size (in bits) of the largest OpenCL built-in data type supported by the device (long16 in FULL profile, long16 or int16 in EMBEDDED profile) for devices that are not of type CL_DEVICE_TYPE_CUSTOM. At the moment, all known devices that support user pointers require CPU page alignment for buffers created from user pointers, so just query that from sysconf. v3: Use std::max instead of MAX2 (Francisco) Add missing unistd include v2: Use system page size instead of a new pipe cap Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by (v2): Jan Vesely <[email protected]>
* mesa: optimize _mesa_attr_zero_aliases_vertex()Brian Paul2017-08-213-12/+22
| | | | | | | | | | | After the context is initialized, the API and context flags won't change. So, we can compute whether vertex attribute 0 aliases vertex position just once. This should make the glVertexAttrib*() functions a little quicker. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vbo: use new _is_vertex_position() helper in vbo_attrib_tmp.hBrian Paul2017-08-211-36/+46
| | | | | | | Makes the code a bit more understandable. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vbo: make vbo_bind_arrays() staticBrian Paul2017-08-212-3/+1
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* svga: replace gotos with conditionals in array drawing codeBrian Paul2017-08-212-32/+32
| | | | | | No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* llvmpipe: add some whitespace between functions in lp_texture.cBrian Paul2017-08-211-0/+3
| | | | Trivial.
* mesa: formatting clean-up in syncobj.cBrian Paul2017-08-211-10/+13
| | | | Line wrap to 78 columns, etc. Trivial.
* svga: whitespace clean-up in svga_draw_private.hBrian Paul2017-08-211-29/+27
| | | | Trivial.
* gallium/docs: remove old llvmpipe TODOTimothy Arceri2017-08-221-14/+0
| | | | | | | Features are already covered by features.txt like all the other drivers. Reviewed-by: Eric Engestrom <[email protected]>
* mesa: fix ES only draw if we have vertex positionsTimothy Arceri2017-08-221-2/+2
| | | | | | | | | | | | This code was separated from the validation code so it could use used with KHR_no_error paths. The return values were inverted to reflect the name of the helper, but here the condtion was mistakenly inverted rather than the return value. Fixes: 4df2931a87fe (mesa/vbo: move some Draw checks out of validation) Reported-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: Add prototype for udivmod64()Matt Turner2017-08-211-0/+3
| | | | Reviewed-by: Jordan Justen <[email protected]>
* glsl: Mark functions staticMatt Turner2017-08-2111-36/+36
| | | | | | Cuts 3224 bytes of .text Reviewed-by: Jordan Justen <[email protected]>
* i965: Mark functions staticMatt Turner2017-08-213-20/+21
| | | | | | Cuts 300 bytes of .text Reviewed-by: Jordan Justen <[email protected]>
* i965/vec4: Use 'class' src_reg, rather than 'struct' src_regMatt Turner2017-08-211-1/+1
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965/vec4: Return float from spill_cost_for_type()Matt Turner2017-08-211-1/+1
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Move clamp_int64() inside the IVB checkMatt Turner2017-08-211-1/+1
| | | | | | It's only used in the gen7_cmd_buffer_emit_scissor() function. Reviewed-by: Jordan Justen <[email protected]>
* glsl: Remove unused private fieldsMatt Turner2017-08-212-5/+2
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Don't compare unsigned for < 0Matt Turner2017-08-211-1/+1
| | | | | | | | | | | | | The INTEL_performance_query spec says "Performance counter id 0 is reserved as an invalid counter." GLuint counterid_to_index(GLuint counterid) just returns counterid - 1, so with unsigned overflow rules, it will generate 0xFFFFFFFF given an input of 0. 0xFFFFFFFF will trigger the counterIndex >= queryNumCounters check, so the code worked as is. It just contained a useless comparison. Reviewed-by: Jordan Justen <[email protected]>
* egl: Fix inclusion of egl.h+mesa_glinterop.hMatt Turner2017-08-212-2/+2
| | | | | | | | Previously clang would warn about redefinition of typedef EGLDisplay. Avoid this by adding preprocessor guards to mesa_glinterop.h and including it after EGL.h is indirectly included. Reviewed-by: Jordan Justen <[email protected]>
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-212-1/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: don't set up and don't call the fetch shader if there are no VS inputsMarek Olšák2017-08-213-1/+7
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* i965: Optimize reading the destination typeMatt Turner2017-08-211-1/+3
| | | | | | | | | | | | | brw_hw_type_to_reg_type() needs to know only whether the file is BRW_IMMEDIATE_VALUE or not, which is not a valid file for the destination. gcc and clang will evaluate __builtin_strcmp() at compile time, so we can use it to pass a constant file for the destination. text data bss dec hex filename 7816214 346248 420496 8582958 82f72e i965_dri.so before 7816070 346248 420496 8582814 82f69e i965_dri.so after Reviewed-by: Scott D Phillips <[email protected]>
* i965: Mark brw_hw_type_to_reg_type() as a pure functionMatt Turner2017-08-211-1/+7
| | | | | | | | text data bss dec hex filename 7816886 346248 420496 8583630 82f9ce i965_dri.so before 7816214 346248 420496 8582958 82f72e i965_dri.so after Reviewed-by: Scott D Phillips <[email protected]>
* i965: Hide the register type hardware encodingsMatt Turner2017-08-212-31/+31
| | | | | | So we stop mixing them with the logical enum. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Stop using hardware register types directlyMatt Turner2017-08-214-158/+113
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.cMatt Turner2017-08-213-39/+45
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Move brw_reg_type_letters() as wellMatt Turner2017-08-216-33/+37
| | | | | | | And add "to_" to the name for consistency with the other functions in this file. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Switch to using the logical register typesMatt Turner2017-08-212-21/+19
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add functions to abstract access to register typesMatt Turner2017-08-212-51/+79
| | | | | | | | | | | | | | | | | | Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions provided access to the hardware encodings for the register types. We often mixed these with the logical BRW_REGISTER_TYPE_* enums (which themselves used to be the hardware format!) with bad results. With that functionality now available with the hw_ versions (see previous commit), we now add functions that take the logical BRW_REGISTER_TYPE_* enums and convert into the hardware format and vice versa. To do the conversion we also have to provide the file. Note the asymmetry between the two functions: the new getter reads the file from the instruction word, and to ensure that is always set the setter writes both the file and the type. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Rename brw_inst's functions that access the register typeMatt Turner2017-08-217-99/+99
| | | | | | Put hw_ in the name so that it's clear these are the hardware encodings. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Index brw_hw_reg_type_to_size()'s table by logical typeMatt Turner2017-08-211-39/+19
| | | | | | I'll be transitioning everything to use the logical types. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add a brw_hw_type_to_reg_type() functionMatt Turner2017-08-212-0/+29
| | | | | | Will be used in later commits. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Use a common table to translate logical to hardware typesMatt Turner2017-08-211-36/+29
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Extract functions dealing with register types to separate fileMatt Turner2017-08-215-140/+209
| | | | | | | | | | I'm going to encapsulate all of the logic dealing with register types in this file. Rename the parameters for the hardware encodings from type -> hw_type at the same time. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Reverse file/type arguments to register type functionsMatt Turner2017-08-214-13/+15
| | | | | | | I think of the initial arguments as "state" and the last as the actual subject. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add support for disassembling 64-bit integer immediatesMatt Turner2017-08-212-0/+13
| | | | | | | After the last patch converted things into enums, I helpfully got a compiler warning about these missing from the switch statement. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-216-129/+144
| | | | | | | The hardware encodings often mean different things depending on whether the source is an immediate. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Reorder brw_reg_type enum valuesMatt Turner2017-08-215-26/+21
| | | | | | | | | | | These vaguely corresponded to the hardware encodings, but that is purely historical at this point. Reorder them so we stop making things "almost work" when mixing enums. The ordering has been closen so that no enum value is the same as a compatible hardware encoding. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Validate destination restrictions with vector immediatesMatt Turner2017-08-213-12/+141
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Don't let raw-move check be tricked by immediate vector typesMatt Turner2017-08-211-3/+10
| | | | | | | UB and B type encodings are the same as UV and VF. Noticed when writing the following patch. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Only change type of 0.0f to VF if destination stride == 1Matt Turner2017-08-211-1/+2
| | | | | | | | | | The destination stride must be equivalent to a dword if VF is used. Also, since the only compaction table entires with "i:vf" have the destination as "r:f" specifically check that the destination is of type float. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Remove CONT/BREAK from instruction compaction testMatt Turner2017-08-211-4/+0
| | | | | | | These cannot be compacted. A similar mistake was fixed in commit 90eaf01616a8 Reviewed-by: Scott D Phillips <[email protected]>
* i965: Test instruction compaction on all supported GensMatt Turner2017-08-211-8/+42
| | | | | | | | Note that there's no point in testing on G45, since its compaction is the same as Gen5. Same logic applies to Gen7 variants and low-power parts. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Silence signed/unsigned comparison warningMatt Turner2017-08-211-1/+1
| | | | Reviewed-by: Scott D Phillips <[email protected]>
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