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* amd: replace major llvm version checks with LLVM_VERSION_MAJOREric Engestrom2019-09-0610-26/+39
* svga: replace binary HAVE_LLVM checks with LLVM_AVAILABLEEric Engestrom2019-09-061-1/+1
* r600: replace binary HAVE_LLVM checks with LLVM_AVAILABLEEric Engestrom2019-09-061-6/+2
* aux/draw: replace binary HAVE_LLVM checks with LLVM_AVAILABLEEric Engestrom2019-09-068-26/+26
* gallivm: replace `0x` version print with actual version stringEric Engestrom2019-09-061-2/+3
* anv,iris: L3ALLOC register replaces L3CNTLREG for gen12Jordan Justen2019-09-063-9/+29
* intel/gen12: Add L3 configurationsAnuj Phogat2019-09-061-1/+12
* util: include u_endian.h in u_math.hRhys Perry2019-09-061-0/+1
* anv: Bump maxComputeWorkgroupSizeJason Ekstrand2019-09-061-4/+6
* intel: Stop redirecting state cache to command streamer cache sectionKenneth Graunke2019-09-063-23/+0
* iris: Invalidate state/texture/constant caches after STATE_BASE_ADDRESSKenneth Graunke2019-09-061-4/+55
* freedreno/a6xx: Implement primitive count queries on GPUKristian H. Kristensen2019-09-0615-18/+128
* freedreno/a6xx: Let the GPU track streamout offsetsKristian H. Kristensen2019-09-064-19/+36
* llvmpipe: fix CALLOC vs. free mismatchesRoland Scheidegger2019-09-062-4/+5
* radv/gfx10: determine the number of vertices per primitive for TESSamuel Pitoiset2019-09-061-1/+16
* nir/lower_io_to_vector: add flat modeRhys Perry2019-09-061-47/+204
* nir/lower_io_to_vector: allow FS outputs to be vectorizedRhys Perry2019-09-062-27/+33
* radv/gfx10: make use the output usage mask when exporting NGG GS paramsSamuel Pitoiset2019-09-061-3/+8
* radv/gfx10: account for the subpass view for the NGG GS storageSamuel Pitoiset2019-09-061-0/+3
* panfrost/ci: Increase timeoutsTomeu Vizoso2019-09-061-2/+2
* panfrost/ci: Use special runner for LAVA jobsTomeu Vizoso2019-09-061-9/+1
* panfrost/ci: Re-add support for armhfTomeu Vizoso2019-09-064-28/+39
* radv: calculate esgs_itemsize in the shader info passSamuel Pitoiset2019-09-062-14/+20
* radv: calculate the GSVS vertex size in the shader info passSamuel Pitoiset2019-09-062-15/+11
* radv: gather primitive ID in the shader info passSamuel Pitoiset2019-09-062-3/+17
* radv: gather layer in the shader info passSamuel Pitoiset2019-09-062-10/+20
* radv: gather viewport in the shader info passSamuel Pitoiset2019-09-062-8/+3
* radv: gather pointsize in the shader info passSamuel Pitoiset2019-09-062-8/+3
* radv: gather clip/cull distances in the shader info passSamuel Pitoiset2019-09-062-21/+25
* radv: move ac_fill_shader_info() to radv_nir_shader_info_pass()Samuel Pitoiset2019-09-062-45/+38
* radv: merge radv_shader_variant_info into radv_shader_infoSamuel Pitoiset2019-09-066-293/+275
* radeon: Fix mjpeg issue for ARCTURUSZhu, James2019-09-061-0/+1
* radeon/vcn: add RENOIR VCN decode supportLeo Liu2019-09-061-4/+4
* glsl: Fix unroll of do{} while(false) like loopsDanylo Piliaiev2019-09-062-17/+41
* tgsi_to_nir: Remove dependency on libglsl.Timur Kristóf2019-09-062-14/+18
* nir: Carve out nir_lower_samplers from GLSL code.Timur Kristóf2019-09-065-127/+159
* radeonsi: Release storage for smda_uploads when the context is destroyedGert Wollny2019-09-061-0/+1
* android: mesa: revert "Enable asm unconditionally"Mauro Rossi2019-09-062-0/+4
* radv/gfx10: always set ballot_mask_bits to 64Samuel Pitoiset2019-09-061-2/+1
* nir/lower_explicit_io: Handle 1 bit loads and storesCaio Marcelo de Oliveira Filho2019-09-051-9/+24
* Revert "intel/fs: Move the scalar-region conversion to the generator."Jason Ekstrand2019-09-064-5/+5
* intel/fs: Fix FB write inst groupsJason Ekstrand2019-09-061-1/+1
* lima/ppir: don't lower phis to scalarVasily Khoruzhick2019-09-051-1/+0
* freedreno/a2xx: formats updateJonathan Marek2019-09-065-250/+106
* freedreno/a2xx: fix depth gmem restoreJonathan Marek2019-09-061-15/+12
* freedreno/a2xx: implement polygon offsetJonathan Marek2019-09-062-0/+14
* freedreno/a2xx: fix SRC_ALPHA_SATURATE for alpha blend functionJonathan Marek2019-09-061-1/+6
* freedreno/a2xx: ir2: update register state in scalar insertJonathan Marek2019-09-061-0/+6
* freedreno/a2xx: ir2: fix incorrect instruction reorderingJonathan Marek2019-09-061-0/+16
* freedreno/a2xx: ir2: check opcode on the right instruction in export cpJonathan Marek2019-09-061-1/+1
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