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* i965: Enable the constant propagation code.Eric Anholt2010-10-061-2/+0
| | | | A debug disable had slipped in.
* r600g: avoid segfault due to unintialized list pointerJerome Glisse2010-10-062-7/+9
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: Fix sprite coord perspective interpolation of Q.José Fonseca2010-10-061-9/+3
| | | | | Q coordinate's coefficients also need to be multiplied by w, otherwise it will have 1/w, causing problems with TXP.
* llvmpipe: Fix perspective interpolation for point sprites.José Fonseca2010-10-061-17/+54
| | | | | | | | | | | Once a fragment is generated with LP_INTERP_PERSPECTIVE set for an input, it will do a divide by w for that input. Therefore it's not OK to treat LP_INTERP_PERSPECTIVE as LP_INTERP_LINEAR or vice-versa, even if the attribute is known to not vary. A better strategy would be to take the primitive in consideration when generating the fragment shader key, and therefore avoid the per-fragment perspective divide.
* llvmpipe: Dump a few missing shader key flags.José Fonseca2010-10-061-0/+7
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* llvmpipe: make debug_fs_variant respect variant->nr_samplersKeith Whitwell2010-10-061-25/+23
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* retrace: Handle clear_render_target and clear_depth_stencil.José Fonseca2010-10-061-0/+9
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* r600g: add evergreen stencil support.Dave Airlie2010-10-062-2/+24
| | | | this sets the stencil up for evergreen properly.
* r600g: userspace fence to avoid kernel call for testing bo busy statusJerome Glisse2010-10-056-47/+103
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* st/mesa: replace assertion w/ conditional in framebuffer invalidationBrian Paul2010-10-051-2/+11
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=30632 NOTE: this is a candidate for the 7.9 branch.
* r600g: simplify block relocationJerome Glisse2010-10-053-12/+9
| | | | | | | Since flush rework there could be only one relocation per register in a block. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use dirty list to track dirty blocksBas Nieuwenhuizen2010-10-054-8/+33
| | | | Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty.
* nv50: fix always true conditional in shader optimizationNicolas Kaiser2010-10-051-1/+1
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* r600g: improve bo flushingJerome Glisse2010-10-054-822/+825
| | | | | | | | | Flush read cache before writting register. Track flushing inside of a same cs and avoid reflushing same bo if not necessary. Allmost properly force flush if bo rendered too and then use as a texture in same cs (missing pipeline flush dunno if it's needed or not). Signed-off-by: Jerome Glisse <[email protected]>
* r600g: store reloc information in bo structureJerome Glisse2010-10-052-23/+16
| | | | | | | Allow fast lookup of relocation information & id which was a CPU time consumming operation. Signed-off-by: Jerome Glisse <[email protected]>
* pb: fix numDelayed accountingDave Airlie2010-10-051-0/+1
| | | | we weren't decreasing when removing from the list.
* r600g: avoid unneeded bo waitDave Airlie2010-10-051-1/+5
| | | | | | if we know the bo has gone not busy, no need to add another bo wait thanks to Andre (taiu) on irc for pointing this out.
* r600g: drop use_mem_constant.Dave Airlie2010-10-059-14/+3
| | | | since we plan on using dx10 constant buffers everywhere.
* r600g: drop mman allocatorDave Airlie2010-10-053-8/+1
| | | | we don't use this since constant buffers are now being used on all gpus.
* r600g: add bo busy backoff.Dave Airlie2010-10-052-0/+15
| | | | | | When we go to do a lot of bos in one draw like constant bufs we need to avoid bouncing off the busy ioctl, this mitigates by backing off on busy bos for a short amount of times.
* pb: don't keep checking buffers after first busyDave Airlie2010-10-051-13/+19
| | | | | If we assume busy buffers are added to the list in order its unlikely we'd fine one after the first busy one that isn't busy.
* r600g: add bo fenced list.Dave Airlie2010-10-053-0/+43
| | | | | this just keeps a list of bos submitted together, and uses them to decide bo busy state for the whole group.
* swrast: fix choose_depth_texture_level() to respect mipmap filtering stateBrian Paul2010-10-041-5/+10
| | | | NOTE: this is a candidate for the 7.9 branch.
* r300g: fix microtiling for 16-bits-per-channel formatsMarek Olšák2010-10-051-3/+3
| | | | | | These texture formats (like R16G16B16A16_UNORM) were untested until now because st/mesa doesn't use them. I am testing this with a hacked st/mesa here.
* i965: Add support for gen6 FB writes to the new FS.Eric Anholt2010-10-042-3/+22
| | | | | This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
* i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.Eric Anholt2010-10-041-1/+1
| | | | It instead sensibly appears in the src0 slot.
* i965: Add initial folding of constants into operand immediate slots.Eric Anholt2010-10-041-0/+90
| | | | | | We could try to detect this in expression handling and do it proactively there, but it seems like less logic to do it in one optional pass at the end.
* i965: Add trivial dead code elimination in the new FS backend.Eric Anholt2010-10-041-2/+50
| | | | | | | The glsl core should be handling most dead code issues for us, but we generate some things in codegen that may not get used, like the 1/w value or pixel deltas. It seems a lot easier this way than trying to work out up front whether we're going to use those values or not.
* i965: Be more conservative on live interval calculation.Eric Anholt2010-10-041-3/+11
| | | | This also means that our intervals now highlight dead code.
* r600g: Fix SCons build.Vinson Lee2010-10-041-1/+1
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* r600g: remove dead label & fix indentationJerome Glisse2010-10-041-11/+9
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: rename radeon_ws_bo to r600_boJerome Glisse2010-10-042-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use r600_bo for relocation argument, simplify codeJerome Glisse2010-10-044-19/+29
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: allow r600_bo to be a sub allocation of a big boJerome Glisse2010-10-046-28/+37
| | | | | | | Add bo offset everywhere needed if r600_bo is ever a sub bo of a bigger bo. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: rename radeon_ws_bo to r600_boJerome Glisse2010-10-0412-86/+86
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* nvfx: Pair os_malloc_aligned() with os_free_aligned().Krzysztof Smiechowicz2010-10-041-1/+1
| | | | From AROS.
* r600g: TODO domain managementDave Airlie2010-10-041-2/+2
| | | | | no wonder it was slow, the code is deliberately forcing stuff into GTT, we used to have domain management but it seems to have disappeared.
* r600g: fix wwarning in bo_map functionDave Airlie2010-10-041-0/+1
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* r600g: the code to check whether a new vertex shader is needed was wrongDave Airlie2010-10-041-1/+3
| | | | | | | this code was memcmp'ing two structs, but refcounting one of them afterwards, so any subsequent memcmp was never going to work. again this stops unnecessary uploads of vertex program,
* r600g: break out of search for reloc bo after finding it.Dave Airlie2010-10-041-0/+1
| | | | this function was taking quite a lot of pointless CPU.
* i965: Fix glean/texSwizzle regression in previous commit.Eric Anholt2010-10-031-18/+18
| | | | Easy enough patch, who needs a full test run. Oh, that's right. Me.
* i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.Eric Anholt2010-10-021-1/+32
| | | | | | | | | | The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't apply to shadow compares, which always return an intensity value. The texture swizzles can do the job for us. Fixes: glsl1-shadow2D(): 1 glsl1-shadow2D(): 3
* i965: Add support for EXT_texture_swizzle to the new FS backend.Eric Anholt2010-10-021-0/+21
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* r300g: add support for L8A8 colorbuffersMarek Olšák2010-10-021-0/+3
| | | | | Blending with DST_ALPHA is undefined. SRC_ALPHA works, though. I bet some other formats have similar limitations too.
* r300g: add support for R8G8 colorbuffersMarek Olšák2010-10-021-1/+11
| | | | | | | | The hw swizzles have been obtained by a brute force approach, and only C0 and C2 are stored in UV88, the other channels are ignored. R16G16 is going to be a lot trickier.
* mesa/st: initial attempt at RG support for gallium driversDave Airlie2010-10-024-1/+93
| | | | passes all piglit RG tests with softpipe.
* i965: Fix incorrect batchbuffer size in gen6 clip state command.Kenneth Graunke2010-10-011-1/+0
| | | | FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
* i965: Don't try to emit code if we failed register allocation.Eric Anholt2010-10-011-1/+2
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* i965: Fix off-by-ones in handling the last members of register classes.Eric Anholt2010-10-011-5/+5
| | | | | | | Luckily, one of them would result in failing out register allocation when the other bugs were encountered. Applies to glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still fails register allocation, but now legitimately.
* i965: Add a sanity check for register allocation sizes.Eric Anholt2010-10-011-0/+5
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