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* virgl: drop unused format fieldDave Airlie2019-08-262-2/+0
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* lima/ppir: enable vectorize optimizationErico Nunes2019-08-251-0/+5
| | | | | | | | | | pp has vector units and some operations can be optimized when bundled together. Benchmarking this with piglit shaders shows that the instruction count can be greatly reduced on many examples with vectorize. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: lower selects to scalarsErico Nunes2019-08-251-0/+5
| | | | | | | | | nir vec4 fcsel assumes that each component of the condition will be used to select the same component from the options, but pp can't implement that since it only has 1 component for the condition. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima: fix ppir spill stack allocationErico Nunes2019-08-254-9/+25
| | | | | | | | | | | | The previous spill stack was fixed and too small, and caused instability in programs requiring spilling for roughly more than one value. This patch adds a dynamic calculation of the buffer size based on stack utilization and switches it to a separate allocation at flush time that will fit the shader that requires the largest buffer. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* intel/fs: Drop the gl_program from fs_visitorJason Ekstrand2019-08-2515-31/+17
| | | | | | | | | It's not used by anything anymore now that so much lowering has been moved into NIR. Sadly, we still need on in brw_compile_gs() for geometry shaders on Sandy Bridge. Short of a lot of pointless work, that one's probably not going away. Reviewed-by: Kenneth Graunke <[email protected]>
* lima: move format handling to unified placeQiang Yu2019-08-258-103/+190
| | | | | | | | | Create a unified table to handle pipe format to texture and render target format lookup. Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
* radv: Change memory type order for GPUs without dedicated VRAMAlex Smith2019-08-241-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | Put the uncached GTT type at a higher index than the visible VRAM type, rather than having GTT first. When we don't have dedicated VRAM, we don't have a non-visible VRAM type, and the property flags for GTT and visible VRAM are identical. According to the spec, for types with identical flags, we should give the one with better performance a lower index. Previously, apps which follow the spec guidance for choosing a memory type would have picked the GTT type in preference to visible VRAM (all Feral games will do this), and end up with lower performance. On a Ryzen 5 2500U laptop (Raven Ridge), this improves average FPS in the Rise of the Tomb Raider benchmark by up to ~30%. Tested a couple of other (Feral) games and saw similar improvement on those as well. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: 19.2 <[email protected]> (Bas: CCing this to 19.2-rc due to high impact and limited complexity)
* lima/ppir: print register index and components number for spilled registerVasily Khoruzhick2019-08-241-1/+3
| | | | | | | | | It can be useful for debugging purposes Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add control flow supportVasily Khoruzhick2019-08-246-23/+168
| | | | | | | | | | This commit adds support for nir_jump_instr, if and loop nir_cf_nodes. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add better liveness analysisVasily Khoruzhick2019-08-245-74/+225
| | | | | | | | | | | Add better liveness analysis that was modelled after one in vc4. It uses live ranges and is aware of multiple blocks which is prerequisite for adding CF support Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: validate shader outputsVasily Khoruzhick2019-08-241-0/+13
| | | | | | | | Mali4x0 supports only gl_FragColor. gl_FragDepth is not supported. Check that we don't get anything but gl_FragColor in shader outputs. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: turn store_color into ALU nodeVasily Khoruzhick2019-08-234-61/+27
| | | | | | | | | | | | | We don't have a special OP to store color in PP, all we need to do is to store gl_FragColor into reg0, thus it's just a mov and therefore ALU node. Yet we still need to indicate that it's store_color op so regalloc ignores its destination. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: create ppir block for each corresponding NIR blockVasily Khoruzhick2019-08-232-4/+49
| | | | | | | | | | | Create ppir block for each corresponding NIR block and populate its successors. It will be used later in liveness analysis and in CF support Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add dummy opVasily Khoruzhick2019-08-233-5/+21
| | | | | | | | | | | | | | | | We can get following from NIR: (1) r1 = r2 (2) r2 = ssa1 Note that r2 is read before it's assigned, so there's no node for it in comp->var_nodes. We need to create a dummy node in this case which sole purpose is to hold ppir_dest with reg in it. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add write after read deps for registersVasily Khoruzhick2019-08-231-2/+25
| | | | | | | | | | | | | | | For cases like: (1) r1 = r2 (2) r2 = ssa1 We need to add (1) as dependency of (2), otherwise scheduler may reorder them. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: fix ordering depsVasily Khoruzhick2019-08-231-6/+8
| | | | | | | | | | | | | | | | | There can be several root nodes, i.e.: (1) r0 = r1 (2) r2 = r3 (3) branch if (ssa1) We need to make (3) depend on (1) and (2), old code added dependency only for (2), and (1) was kept as root node since there is no branch/discard or store color between two movs. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: set write mask for texture loads if dest is regVasily Khoruzhick2019-08-231-1/+5
| | | | | | | | | | Destination for texture load can be a reg, so we need to set write mask in this case Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: add support for unconditional branches and condition negationVasily Khoruzhick2019-08-234-8/+34
| | | | | | | | | | | | | | | We need 'negate' modifier for branch condition to minimize branching. Idea is to generate following: current_block: { ...; if (!statement) branch else_block; } then_block: { ...; branch after_block; } else_block: { ... } after_block: { ... } Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: clone ld_{uni,tex,var} into each blockVasily Khoruzhick2019-08-234-5/+103
| | | | | | | | | | | | | | | ppir_lower_load() and ppir_lower_load_texture() assume that node is in the same block as its successors, fix it by cloning each ld_uni and ld_tex to every block. It also reduces register pressure since values never cross block boundaries and thus never appear in live_in or live_out of any block, so do it for varyings as well. Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: refactor const loweringVasily Khoruzhick2019-08-236-128/+99
| | | | | | | | | | | Const nodes are now cloned for each user, i.e. const is guaranteed to have exactly one successor, so we can use ppir_do_one_node_to_instr() and drop insert_to_each_succ_instr() Tested-by: Andreas Baierl <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* anv: Only re-emit non-dynamic state that has changed.Rafael Antognolli2019-08-232-24/+50
| | | | | | | | | | | | | | | | | | On commit f6e7de41d7b, we started emitting 3DSTATE_LINE_STIPPLE as part of the non-dynamic state. That gets re-emitted every time we bind a new VkPipeline. But that instruction is non-pipelined, and it caused a perf regression of about 9-10% on Dota2. This commit makes anv_dynamic_state_copy() return a mask with only the state that has changed when copying it. 3DSTATE_LINE_STIPPLE won't be emitted anymore unless it has changed, fixing the problem above. v2: Improve commit message and add documentation about skipped checks (Jason) Fixes: f6e7de41d7b ("anv: Implement VK_EXT_line_rasterization") Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* pan/decode: Validate and quiet helper invocation flagAlyssa Rosenzweig2019-08-231-1/+8
| | | | | | | | We can statically determine from the disassembly if helper invocations will be needed, so we can validate the corresponding bit in the cmdstream and thus avoid printing the bit itself in the decode. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Analyze helper invocationsAlyssa Rosenzweig2019-08-232-0/+22
| | | | | | | | We check for texture ops which calculate derivatives (either explicitly via dFd* or implicitly) and mark the shader as requiring helper invocations. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* util: fix compilation on macosLionel Landwerlin2019-08-231-1/+1
| | | | | | | | | | timespec_get() is not available on macos, we need to pull in the include/c11/threads_posix.h helper. Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103674 Fixes: e2d761de03 ("util: drop final reference to p_compiler.h") Reviewed-by: Eric Engestrom <[email protected]>
* i965: Silence brw_blorp uninitialized warningCaio Marcelo de Oliveira Filho2019-08-231-1/+1
| | | | | | | | | | The variables level and start_layer are not initialized, then initialized if we have a BUFFER_BIT_DEPTH set. We assert on them later using the same check. This should be enough but GCC 9.1.1 is not convinced, so let's initialize the variables. Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* tgsi: Remove unused localCaio Marcelo de Oliveira Filho2019-08-231-1/+0
| | | | | | | | Code that used it was removed in 4ebe6b2e72e ("tgsi: Drop the SSE2 constants setup that's been dead code since 2011.") Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Guard GEN9-only function in Iris state to avoid warningCaio Marcelo de Oliveira Filho2019-08-231-0/+2
| | | | | Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/decoders: Avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2019-08-231-2/+2
| | | | | | | | | Initialize `next_batch_addr` and `second_level`. If the batch is well formed, those values will be overriden, if not, they are as good as uninitialized garbage. Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/glsl: Fix warning about unused functionCaio Marcelo de Oliveira Filho2019-08-231-1/+3
| | | | | | | | | | The helper check_node_type() is only used when DEBUG is set (in the function below), but ASSERTED macro uses NDEBUG. So just guard the helper with #ifdef. If we see more such cases we might consider a ASSERTED-like macro for the DEBUG case. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Drop unused local variableCaio Marcelo de Oliveira Filho2019-08-231-1/+0
| | | | | | | | Leftover from 021fa28163a ("xintel/nir: Add a helper for getting BRW_AOP from an intrinsic"). Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1Caio Marcelo de Oliveira Filho2019-08-231-1/+3
| | | | | | | | | | | | | | | Compiler can't see that d is initialized. ../src/intel/compiler/brw_vec4_nir.cpp: In function ‘int brw::try_immediate_source(const nir_alu_instr*, brw::src_reg*, bool, const gen_device_info*)’: ../src/intel/compiler/brw_vec4_nir.cpp:984:12: warning: ‘d’ may be used uninitialized in this function [-Wmaybe-uninitialized] 984 | d = MAX2(-d, d); Assert that we expect at least one component -- hence d going to be set. That by itself is not enough, so also zero initialize the variable. Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: additional query fixesAndres Rodriguez2019-08-171-7/+8
| | | | | | | | | Make sure we read the updated data from the gpu in cases where WAIT_BIT is not set. Cc: 19.1 19.2 <[email protected] Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: Fix large timeout handling in rel2abs()Kenneth Graunke2019-08-231-13/+14
| | | | | | | | | | | ...by copying the implementation of anv_get_absolute_timeout(). Appears to fix a CTS test with 32-bit builds: GTF-GL46.gtf32.GL3Tests.sync.sync_functionality_clientwaitsync_flush Fixes: f459c56be6b ("iris: Add fence support using drm_syncobj") Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* iris: Set MOCS in all STATE_BASE_ADDRESS commandsKenneth Graunke2019-08-231-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | Rafael Antognolli tracked down a performance gap between i965 and iris in Synmark2's OglCSDof microbenchmark, noting that iris was performing substantially more memory reads and writes, with substantially fewer L3 hits. He suggested that something might be wrong with MOCS, or L3 configs, at which point I came up with a theory... It would appear that the STATE_BASE_ADDRESS command updates the MOCS settings for various base addresses even if you don't specify the "Modify Enable" bit for that address. Until now, we had been setting only the MOCS for bases we intended to change, leaving the others "blank" which is MOCS table entry 0, which is uncached. Most data access has a more specific MOCS (e.g. in SURFACE_STATE), but scratch access uses the Stateless Data Port Access MOCS from STATE_BASE_ADDRESS. So this meant all scratch access was uncached. Improves performance in Synmark2's OglCSDof by 2x, bringing iris on par with the existing i965 driver. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* glx: Fix up glXQueryGLXPbufferSGIX on macOS.Vinson Lee2019-08-231-1/+0
| | | | | | | | | | | | | Fix this build error on macOS. ../src/glx/apple/glx_empty.c:158:4: error: void function 'glXQueryGLXPbufferSGIX' should not return a value [-Wreturn-type] return 0; ^ ~ Fixes: 3dd299c3d5b8 ("glx: Sync <GL/glxext.h> with Khronos") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* radeonsi/nir: Rewrite output scanningConnor Abbott2019-08-231-126/+150
| | | | | | | | | Similarly to before, this didn't properly handle varying structs with doubles in them. This doesn't fix any tests, but was noticed while looking at the code. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: Rewrite store intrinsic gatheringConnor Abbott2019-08-231-59/+84
| | | | | | | | | | | The old version wasn't as accurate as it could be, and didn't handle double variables inside structs correctly. Walk the path to compute the actual components affected. In combination with the previous commit fixes KHR-GL45.enhanced_layouts.varying_structure_locations. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: Add const_index when loading GS inputsConnor Abbott2019-08-231-1/+1
| | | | | | This fixes loading GS inputs in structures or arrays. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: Don't add const offset to indirectConnor Abbott2019-08-231-19/+6
| | | | | | | | | This is already done in get_deref_offset() in the common code. We were adding it twice accidentally. Fixes KHR-GL45.enhanced_layouts.varying_array_locations. Reviewed-by: Marek Olšák <[email protected]>
* ac/nir: Assert GS input index is constantConnor Abbott2019-08-231-0/+1
| | | | | | If it's not we silently ignore indir_index which is definitely a bug. Reviewed-by: Marek Olšák <[email protected]>
* ac/nir: Handle const array offsets in get_deref_offset()Connor Abbott2019-08-231-6/+11
| | | | | | | | | | | Some users of this function (e.g. GS inputs) currently only work with constant offsets. We got lucky since all the tests used an array index of 0, so the non-constant part was always 0. But we still need to handle this. This doesn't fix any CTS test, but was noticed while debugging one. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: Don't recompute num_inputs and num_outputsConnor Abbott2019-08-231-24/+3
| | | | | | Don't repeat what mesa/st already does. Reviewed-by: Marek Olšák <[email protected]>
* st/nir: Fix num_inputs for VS inputsConnor Abbott2019-08-231-3/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radv/gfx10: do not use NGG with NAVI14Samuel Pitoiset2019-08-231-0/+1
| | | | | | Cc: 19.2 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0Samuel Pitoiset2019-08-231-1/+2
| | | | | | | | | Only gfx9 and older use it to get InstanceID in VGPR1. Ported from RadeonSI. Cc: 19.2 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac,radv,radeonsi: remove LLVM 7 supportSamuel Pitoiset2019-08-2313-320/+65
| | | | | | | | Now that LLVM 9 will be released soon, we will only support LLVM 8, 9 and master (10). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl: reset blob cache set/get functions on terminateTapani Pälli2019-08-231-0/+4
| | | | | | | | | Fixes errors seen with eglSetBlobCacheFuncsANDROID on Android when running dEQP that terminates and reinitializes a display. Fixes: 6f5b57093b3 "egl: add support for EGL_ANDROID_blob_cache" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* iris: Avoid unnecessary resolves on transfer mapsKenneth Graunke2019-08-222-16/+31
| | | | | | | | | | We were always resolving the buffer as if we were accessing it via CPU maps, which don't understand any auxiliary surfaces. But we often copy to a temporary using BLORP, which understands compression just fine. So we can avoid the resolve, and accelerate the copy as well. Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls") Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Drop copy format hacks from copy region based transfer path.Kenneth Graunke2019-08-221-16/+5
| | | | | | | | | | | | | | This doesn't work for compressed formats, as the source texture and temporary texture would have different block sizes. (Forcing the driver to always take the GPU path would expose the bug.) Instead, just use the source format for the temporary, and let blorp_copy deal with overrides. The one case where we can't do this is ASTC, because isl won't let us create a linear ASTC surface. Fall back to the CPU paths there for now. Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls") Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Update fast clear colors on Gen9 with direct immediate writes.Kenneth Graunke2019-08-222-9/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gen11 stores the fast clear color in an "indirect clear buffer", as a packed pixel value. Gen9 hardware stores it as a float or integer value, which is interpreted via the format. We were trying to store that in a buffer, for similarity with Icelake, and MI_COPY_MEM_MEM it from there to the actual SURFACE_STATE bytes where it's stored. This unfortunately doesn't work for blorp_copy(), which does bit-for-bit copies, and overrides the format to a CCS-compatible UINT format. This causes the clear color to be interpreted in the overridden format. Normally, we provide the clear color on the CPU, and blorp_blit.c:2611 converts it to a packed pixel value in the original format, then unpacks it in the overridden format, so the clear color we use expands to the bits we originally desired. However, BLORP doesn't support this pack/unpack with an indirect clear buffer, as it would need to do the math on the GPU. On Gen11+, it isn't necessary, as the hardware does the right thing. This patch changes Gen9 to stop using an indirect clear buffer and simply do PIPE_CONTROLs with post-sync write immediate operations to store the new color over the surface states for regular drawing. BLORP continues streaming out surface states, and handles fast clear colors on the CPU. Fixes: 53c484ba8ac ("iris: blorp using resolve hooks") Reviewed-by: Rafael Antognolli <[email protected]>
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