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* mesa: add NULL checking to free_shared_state()Timothy Arceri2017-08-082-31/+65
| | | | | | | | This will allow us to call this function from _mesa_alloc_shared_state() in the case that we run out of memory part way through allocating the state. Reviewed-by: Samuel Pitoiset <[email protected]>
* glapi: per the extension spec, the EXT-suffixed function should be usedIlia Mirkin2017-08-071-10/+0
| | | | | | | | We already expose glMultiDrawElementsBaseVertexEXT as part of the EXT_draw_elements_base_vertex chunk, so this one can just be removed. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* radv: remove semicolon in if(...);Bas Nieuwenhuizen2017-08-081-1/+1
| | | | | | Trivial. Fixes: a6a6146aa91 "radv: Don't allow fmask swizzling for shareable images."
* radv: Fix decompression on multisampled depth buffersAlex Smith2017-08-072-35/+69
| | | | | | | | | | Need to take the sample count into account in the depth decompress and resummarize pipelines and render pass. Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver") Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]>
* radv: Don't allow fmask swizzling for shareable images.Bas Nieuwenhuizen2017-08-071-1/+4
| | | | | | | | Also adds an assert because you never know how the winsys changes, and multiprocess format differences are annoying. Fixes: 1e696b962b7 "radv: add separate fmask tile swizzle counter." Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: fix a compile failure due to disabled assertsMarek Olšák2017-08-071-1/+1
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* radeonsi: use optimal packet order when doing a pipeline syncMarek Olšák2017-08-071-34/+83
| | | | | | | | | | | | Process most new SET packets in parallel with previous draw calls, then flush caches and wait, start the draw, and do L2 prefetches last. This decreases the [CP busy / SPI busy] ratio (verified with GRBM perf counters). In other words, the time window when shaders are idle (between (the wait and the draw) is much shorter now. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: expose the number of decompress calls to the HUDMarek Olšák2017-08-074-7/+20
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename GPU-dma-busy -> GPU-cp-dma-busyMarek Olšák2017-08-074-8/+8
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rename shader_userdata -> shader_pointers where appropriateMarek Olšák2017-08-075-20/+20
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: prefetch VBO descriptors after the first VGT shaderMarek Olšák2017-08-071-17/+63
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a separate dirty mask for prefetchesMarek Olšák2017-08-076-16/+64
| | | | | | | | | | so that we don't rely on si_pm4_state_enabled_and_changed, allowing us to move prefetches after draw calls. v2: ckear the dirty mask after unbinding shaders Tested-by: Dieter Nützel <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: add and use si_pm4_state_enabled_and_changedMarek Olšák2017-08-073-17/+18
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: de-atomize L2 prefetchMarek Olšák2017-08-077-9/+11
| | | | | | | I'd like to be able to move the prefetch call site around. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: align all CE dumps to L2 cache line sizeMarek Olšák2017-08-071-8/+17
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove a tautology sctx->framebuffer.nr_samples >= 1Marek Olšák2017-08-071-2/+1
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: print all members of radeon_info with R600_DEBUG=infoMarek Olšák2017-08-072-3/+15
| | | | | | | also set max_alignment on amdgpu. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl: update the extensions/functions that are enabled for 460Samuel Pitoiset2017-08-072-17/+99
| | | | | | | | Other ones are either unsupported or don't have any helper function checks. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* egl/dri2: add image extension such it's usable by swrast driverGurchetan Singh2017-08-073-2/+5
| | | | | | | | | | | | | | | | | | Otherwise, this extension is not visible to the EGL users who use the swrast driver. This will allow the swrast driver to use eglCreateImageKHR, provided the target is EGL_GL_TEXTURE_2D_KHR or EGL_GL_RENDERBUFFER_KHR. Note we still have to implement the create from render buffer path. v2: add it to optional_core_extensions instead of swrast_core_extensions, so it's not a requirement (Emil) v3: Merge egl/dri2 changes together, also add support for platform_wayland (Emil) Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2)
* st/dri: add drisw image extensionGurchetan Singh2017-08-071-0/+11
| | | | | | | | | Since the revelant functions have been moved to dri_helpers, drisw.c can make use of the extension. Note we have version 6 of the extension, since we want to support createImageFromTexture. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/dri: move some image functions to dri_helpers.cGurchetan Singh2017-08-073-106/+124
| | | | | | | | | These functions will be used both by drisw.c and dri2.c. This patch also moves some headers that can be shared. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/dri: organize order of includers in dri_helpersGurchetan Singh2017-08-071-2/+3
| | | | | | | | Although it doesn't seem like a strict requirement of the code base, we do it when possible and it looks nice. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/dri: change dri_extensions to dri_helpersGurchetan Singh2017-08-075-6/+6
| | | | | | | | These files provide helper structs and functions for dri2.c and drisw.c, and name change better conveys that. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/miptree: Set supports_fast_clear = false in make_shareableJason Ekstrand2017-08-071-0/+1
| | | | | | | | | | | | The make_shareable function deletes the aux buffer and then whacks aux_usage to ISL_AUX_USAGE_NONE but not unsetting supports_fast_clear. Since we only look at supports_fast_clear to decide whether or not to do fast clears, this was causing assertion failures. Reported-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101925 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/miptree: Rework create flagsJason Ekstrand2017-08-078-38/+52
| | | | | | | | | The only one of the three remaining flags that has anything whatsoever to do with layout is TILING_NONE. This commit renames them to MIPTREE_CREATE_*, documents the meaning of each flag, and makes the create functions take an actual enum type so GDB will print them nicely. Reviewed-by: Jordan Justen <[email protected]>
* i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)Jason Ekstrand2017-08-076-24/+8
| | | | | | | The only force tiling flag we really care about is LAYOUT_TILING_NONE. The others don't actually do anything but add confusion. Reviewed-by: Jordan Justen <[email protected]>
* i965/miptree: Delete an unused function declarationJason Ekstrand2017-08-071-5/+0
| | | | | | The implementation of brw_miptree_layout was removed in bf24c3539e4b69. Reviewed-by: Jordan Justen <[email protected]>
* i965/miptree: Call alloc_aux in create_for_boJason Ekstrand2017-08-071-6/+7
| | | | | | | | | | | | Originally, I had moved it to the caller to make some things easier when adding the CCS modifier. However, this broke DRI2 because intel_process_dri2_buffer calls intel_miptree_create_for_bo but never calls intel_miptree_alloc_aux. Also, in hindsight, it should be pretty easy to make the CCS modifier stuff work even if create_for_bo allocates the CCS when DISABLE_AUX is not set. Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* i965/miptree: Delete MIPTREE_LAYOUT_FOR_SCANOUTJason Ekstrand2017-08-073-7/+15
| | | | | | | | | The flag hasn't affected actual surface layout for some time. The only purpose it served was to set bo->cache_coherent = false on the BO used to create the miptree. This is fairly silly because we can just set that directly from the caller where it makes much more sense. Reviewed-by: Jordan Justen <[email protected]>
* i965/miptree: Delete some unused layout flagsJason Ekstrand2017-08-072-10/+2
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965/miptree: Refactor is_mcs_supportedJason Ekstrand2017-08-071-4/+9
| | | | | | | | | We rename it to intel_miptree_supports_mcs and make the function signature match intel_miptree_supports_ccs/hiz. We also move the sample count check into the function so it returns false for single-sampled surfaces. Reviewed-by: Jordan Justen <[email protected]>
* i965/miptree Remove layout_flags parameter form is_mcs_supportedJason Ekstrand2017-08-071-9/+2
| | | | | | | The one caller of is_mcs_supported passes 0 in as the layout_flags unconditionally. Reviewed-by: Jordan Justen <[email protected]>
* intel/isl: Don't align the height of the last array sliceJason Ekstrand2017-08-071-1/+2
| | | | | | | | | | | | | We were calculating the total height of 2D surfaces by multiplying the row pitch by the number of slices. This means that we actually request slightly more space than actually needed since the padding on the last slice is unnecessary. For tiled surfaces this is not likely to make a difference. For linear surfaces, on the other hand, this means we may require additional memory. In particular, this makes the i965 driver reject EGL imports of buffers which do not have this extra padding. Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* intel/isl: Stop padding surfacesJason Ekstrand2017-08-071-117/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The docs contain a bunch of commentary about the need to pad various surfaces out to multiples of something or other. However, all of those requirements are about avoiding GTT errors due to missing pages when the data port or sampler accesses slightly out-of-bounds. However, because the kernel already fills all the empty space in our GTT with the scratch page, we never have to worry about faulting due to OOB reads. There are two caveats to this: 1) There is some potential for issues with caches here if extra data ends up in a cache we don't expect due to OOB reads. However, because we always trash the entire cache whenever we need to move anything between cache domains, this shouldn't be an issue. 2) There is a potential issue if a surface gets placed at the very top of the GTT by the kernel. In this case, the hardware could potentially end up trying to read past the top of the GTT. If it nicely wraps around at the 48-bit (or 32-bit) boundary, then this shouldn't be an issue thanks to the scratch page. If it doesn't, then we need to come up with something to handle it. Up until some of the GL move to ISL, having the padding code in there just caused us to harmlessly use a bit more memory in Vulkan. However, now that we're using ISL sizes to validate external dma-buf images, these padding requirements are causing us to reject otherwise valid images due to the size of the BO being too small. Acked-by: Kenneth Graunke <[email protected]> Tested-by: Tapani Pälli <[email protected]> Tested-by: Tomasz Figa <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "17.2" <[email protected]>
* anv/formats: Allow sampling on depth-only formats on gen7Jason Ekstrand2017-08-071-1/+2
| | | | | | | | | We can't sample from depth-stencil formats but on gen7 but we can sample from depth-only formats. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102024 Reviewed-by: Juan A. Suarez Romero <[email protected]> Cc: [email protected]
* radv: fix MSAA on SI gpus.Dave Airlie2017-08-071-3/+7
| | | | | | | | | | This ports the workaround from radeonsi, that was missing in radv. This fixes Talos rendering when MSAA is enabled on my Tahiti card. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Signed-off-by: Dave Airlie <[email protected]>
* radv: add separate fmask tile swizzle counter.Dave Airlie2017-08-073-3/+11
| | | | | | | | | This mirrors what Marek has done for radeonsi, and uses a separate counter to handle the fmask surface for MSAA MRTs. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix f16->f32 denorm handling for SI/CIK. (v2)Dave Airlie2017-08-071-2/+16
| | | | | | | | | | | | This just copies the code from the -pro shaders, and fixes the tests on CIK. With this CIK passes the same set of conformance tests as VI. Fixes: 83e58b03 (radv: flush f32->f16 conversion denormals to zero. (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* etnaviv: Add support for R8_UNORM texturesWladimir J. van der Laan2017-08-061-1/+1
| | | | | | | | R8_UNORM textures can be emulated by means of L8 and a swizzle. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Implement ICACHEWladimir J. van der Laan2017-08-066-18/+95
| | | | | | | | | | | | | | | This patch adds support for large shaders on GC3000. For example the "terrain" glmark benchmark with a large fragment shader will work after this. If the GPU supports ICACHE, shaders larger than the available state area will be uploaded to a bo of their own and instructed to be loaded from memory on demand. Small shaders will be uploaded in the usual way. This mimics the behavior of the blob. On GPUs that don't support ICACHE, this patch should make no difference. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Unified uniforms supportWladimir J. van der Laan2017-08-063-4/+36
| | | | | | | | | | | | | | GC3000 has changed from a separate store for VS and PS uniforms to a single, unified one. There is backwards compatibilty functionalty, however this does not work correctly together with ICACHE. This patch adds explicit support, although in the simplest way possible: the PS/VS uniforms split is still fixed and hardcoded. It should make no difference on hardware that does not have unified uniform memory. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Update headers from rnndbWladimir J. van der Laan2017-08-061-5/+9
| | | | | Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* fix GL_ARB_spirv_extensions nameIlia Mirkin2017-08-061-1/+1
| | | | Trivial. There is no _gl_ in there.
* radv: Use the correct channel for alpha in resolve srgb conversion.Bas Nieuwenhuizen2017-08-061-1/+1
| | | | | | | | | The argument here is a bitmask, so the old code selected .xy, which got silently truncated to .x when constructing the vec4 from components, instead of using .w. Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader." Reviewed-by: Dave Airlie <[email protected]>
* radv: Only convert linear->srgb in compute resolves.Bas Nieuwenhuizen2017-08-065-79/+54
| | | | | | | | | It justs works with the fragment shader resolve, so no need to do a custom conversion. In fact with SRGB dest, it actually gives wrong results. Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Dave Airlie <[email protected]>
* radv: Don't use SRGB format for image stores during resolve.Bas Nieuwenhuizen2017-08-062-1/+24
| | | | | | | | | These seem to store very bogus results. Luckily there is some code that converts srgb->linear already, so just making the descriptor format UNORM should work. Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader." Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: enable support for EXT_memory_objectAndres Rodriguez2017-08-061-1/+1
| | | | | | | | | v2: fix an indentation error v3: don't enable for r600 Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: generate the same driver UUID as radeonsiAndres Rodriguez2017-08-062-1/+9
| | | | | | | These need to match for interop compatibility queries. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: generate same device UUID as radeonsiAndres Rodriguez2017-08-061-7/+4
| | | | | | | | | | | This is required for interop use cases. The same device must report identical UUIDs through the GL and Vulkan APIs so that users can identify when it is safe to perform a memory object import. v2: use ac helpers to calculate the uuid Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: hook up queries for NUM_TILING_TYPES and TILING_TYPESAndres Rodriguez2017-08-063-0/+47
| | | | | | | | These are just basic implementations. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
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