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* nouveau/codegen: add missing values for OP_TXLQ into the target arraysIlia Mirkin2014-04-192-7/+9
| | | | | | | | | | Also rework things so that if someone were to add an opcode without adjusting the values in these arrays, there will be a compilation error. This fixes a few quadop-related piglit regressions since commit d5faf8e78603. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: change logic for centering of eng2d blit when downsamplingIlia Mirkin2014-04-191-2/+2
| | | | | | | | We want to center the sample. The old code may have been correct given the limited values of ms_x/y, but the new logic should be more intuitive. Note that ms_x can only be 1/2 and ms_y can only be 0/1. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: use 2d blit when src/dst have same number of samplesIlia Mirkin2014-04-191-4/+4
| | | | | | | | | | | The 2D engine should be usable in more cases, but this fixes MS blits between textures with the same MS settings. Otherwise a single sample is selected to be the target texel value. This allows other tests to work that render to a RB and then blit that to a texture for input into a shader that uses sampler2DMS to verify it. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/docs: fix PIPE_CAP_ENDIANNESS delimiter, remove trailing spacesIlia Mirkin2014-04-191-4/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* i965/fs: Implement fs_inst::force_sechalf support on Broadwell.Kenneth Graunke2014-04-183-4/+8
| | | | | | | | | | | | | Back when I originally wrote this code, force_sechalf was only used for Gen4 code, so I didn't bother hooking it up. However, it's used more generally these days. In particular, we use it for computing gl_SamplePosition. Fixes Piglit's spec/ARB_sample_shading/builtin-gl-sample-position tests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77222 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: Allow explicit binding on atomics againChris Forbes2014-04-181-1/+3
| | | | | | | | As of 943b2d52bf5, layout(binding) on an atomic would fail the assertion here. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: fix num banks selection on SI for dma setup (v2)Alex Deucher2014-04-183-24/+19
| | | | | | | | | | | | The number of banks varies based on the tile mode index just like CIK. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=77533 v2: fix ordering for nbanks calculation for consistency Signed-off-by: Alex Deucher <[email protected]>
* i965/fs: Reduce restrictions on interference in register coalescing.Matt Turner2014-04-181-13/+0
| | | | | | | | | | | | | We previously only allowed coalescing registers that interfere (i.e., whose live ranges overlap) if the destination register's live range was entirely inside the source's live range. This is unnecessary -- we only need to check for interfering writes in the intersection of their live ranges. total instructions in shared programs: 1639470 -> 1638453 (-0.06%) instructions in affected programs: 84751 -> 83734 (-1.20%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Give up in interference check if we see a WHILE.Matt Turner2014-04-181-1/+1
| | | | | | | | | | | Rather than any old control flow. Muchnick's algorithm just checks for interfering writes between the MOV and the end of the program. Handling this when you have backward branches is hard, so don't, but there's no reason to bail if you see forward branches. instructions in affected programs: 4270 -> 4248 (-0.52%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Simplify interference scan in register coalescing.Matt Turner2014-04-181-13/+9
| | | | | | | | | | | | | | | We were starting at the beginning of the instruction list, rather than with the MOV instruction itself. This allows us to coalesce after control flow. Excluding the shaders from an unreleased title, the shader-db results: total instructions in shared programs: 1603791 -> 1594215 (-0.60%) instructions in affected programs: 678772 -> 669196 (-1.41%) GAINED: 5 LOST: 0 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Unindent can_coalesce_vars().Matt Turner2014-04-181-27/+28
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Recognize nop-MOV instructions early.Matt Turner2014-04-181-3/+17
| | | | | | | | | | And avoid rewriting other instructions unnecessarily. Removes a few self-moves we weren't able to handle because they were components of a large VGRF. instructions in affected programs: 830 -> 826 (-0.48%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Only sweep NOPs if register coalescing made progress.Matt Turner2014-04-181-7/+9
| | | | | | Otherwise there's nothing to do. Reviewed-by: Kenneth Graunke <[email protected]>
* r600g,radeonsi: don't skip the context flush if a fence should be returnedMarek Olšák2014-04-182-2/+2
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77589
* svga: fix comment for emit_adjusted_vertex_attribs()Brian Paul2014-04-171-3/+3
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* svga: compute need_swvfetch in svga_create_vertex_elements_state()Brian Paul2014-04-173-13/+9
| | | | | | This saves us doing it at state validation time. Reviewed-by: Matthew McClure <[email protected]>
* svga: add VS code to set attribute W component to 1Brian Paul2014-04-175-46/+100
| | | | | | | | | | | | | | | There's a few 3-component vertex attribute formats that have no equivalent SVGA3D_DECLTYPE_x format. Previously, we had to use the swtnl code to handle them. This patch lets us use hwtnl for more vertex attribute types by fetching 3-component attributes as 4-component attributes and explicitly setting the W component to 1. This lets us handle PIPE_FORMAT_R16G16B16_SNORM/UNORM and PIPE_FORMAT_R8G8B8_UNORM vertex attribs without using the swtnl path. Fixes piglit normal3b3s GL_SHORT test. Reviewed-by: Charmaine Lee <[email protected]>
* svga: implement support for signed byte vertex attributesBrian Paul2014-04-176-14/+151
| | | | | | | | | | | | | | There's no SVGA3D_DECLTYPE that directly corresponds to PIPE_FORMAT_R8G8B8_SNORM. Previously, we used the swtnl fallback path to handle this but that's slow and causes invariance issues. Now we fetch the attribute as SVGA3D_DECLTYPE_UBYTE4N and insert some extra VS instructions to remap the attributes from the range [0,1] to the range[-1,1]. Fixes Sauerbraten sw fallback. Fixes piglit normal3b3s-invariance test. Reviewed-by: Charmaine Lee <[email protected]>
* svga: move translated vertex declaration types into svga_velems_stateBrian Paul2014-04-174-40/+45
| | | | | | | Now only translate the formats once in svga_create_vertex_elements_state(). And rename the array and use the proper SVGA3dDeclType type. Reviewed-by: Charmaine Lee <[email protected]>
* Revert "svga: add work-around for Sauerbraten Z fighting issue"Brian Paul2014-04-173-49/+2
| | | | | | | | | | | | This reverts commit c875d6e57a817bb6a8163a8a98ebd2768ee91848. Conflicts: src/gallium/drivers/svga/svga_context.c This work-around will no longer be needed after the next patch which properly supports signed-byte vertex attributes. Reviewed-by: Charmaine Lee <[email protected]>
* svga: use new inst_token_setp() helper functionBrian Paul2014-04-172-12/+26
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* svga: use new inst_token_predicated() helper functionBrian Paul2014-04-172-13/+25
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* i965: Retype pre-Gen6 varying pull load destination to UW.Kenneth Graunke2014-04-171-1/+1
| | | | | | | | | | | | This sets up the proper execution mask for sends in SIMD16 mode. Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2, glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake, which regressed when I enabled SIMD16 pull parameter support in commit b207e88b25e526d0f1ada7b19605b880a27866dc. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Fix error condition for multisample proxy texture targetsAnuj Phogat2014-04-171-3/+13
| | | | | | | | Fixes failures in Khronos OpenGL CTS test proxy_textures_invalid_samples Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add glBlitFramebuffer to commands affected by conditional renderingAnuj Phogat2014-04-171-0/+8
| | | | | | | | Fixes failures in Khronos OpenGL CTS test conditional_render_test9 Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: Add glBlitFramebuffer to commands affected by conditional renderingAnuj Phogat2014-04-171-0/+8
| | | | | | Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Fix component mask and varying_to_slot mapping for gl_ViewportIndexAnuj Phogat2014-04-171-1/+5
| | | | | | | | | | | | | | | | gl_ViewportIndex doesn't get its own varying slot. It is stored in VARYING_SLOT_PSIZ.z. This patch fixes the issue for both gen7 and gen8 because gen7_upload_3dstate_so_decl_list() is shared between them. Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins. Makes new piglit test glsl-1.50-transform-feedback-builtins pass for 'gl_ViewportIndex'. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix component mask and varying_to_slot mapping for gl_LayerAnuj Phogat2014-04-171-4/+14
| | | | | | | | | | | | | | | | gl_Layer doesn't get its own varying slot. It is stored in VARYING_SLOT_PSIZ.y. This patch fixes the issue for both gen7 and gen8 because gen7_upload_3dstate_so_decl_list() is shared between them. Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins. Makes new piglit test glsl-1.50-transform-feedback-builtins pass for 'gl_Layer'. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Put an assertion to check valid varying_to_slot[varying]Anuj Phogat2014-04-171-0/+1
| | | | | | | Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: Added Diag Handler to receive LLVM Error messagesDarren Powell2014-04-173-9/+55
| | | | Reviewed-by: Tom Stellard <[email protected]>
* winsys/radeon: remove some unused codeMarek Olšák2014-04-171-28/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: remove is_handle_added arrayMarek Olšák2014-04-172-30/+34
| | | | | | Use index -1 if a buffer is not added. Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: remove local variable reloc from radeon_get_relocMarek Olšák2014-04-171-5/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: remove parameter reloc from radeon_get_relocMarek Olšák2014-04-172-11/+8
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* util: Add __declspec(noreturn) to _debug_assert_fail().José Fonseca2014-04-171-0/+3
| | | | | | | | Mostly for consistency; as MSVC's static source code analysis doesn't seem to rely on assertions, but instead on different kind of source annotations( http://msdn.microsoft.com/en-us/library/hh916383.aspx ). Reviewed-by: Brian Paul <[email protected]>
* auxiliary/os,auxiliary/util: Fix the `‘noreturn’ function does return` ↵José Fonseca2014-04-172-5/+2
| | | | | | | | | | | | | | | | warning. Now that _debug_assert_fail() has the noreturn attribute, it is better that execution truly never returns. Not just for sake of silencing the warning, but because the code at the return IP address may be invalid or lead to inconsistent results. This removes support for the GALLIUM_ABORT_ON_ASSERT debugging environment variable, but between the usefulness of GALLIUM_ABORT_ON_ASSERT and better static code analysis I think better static code analysis wins. Reviewed-by: Brian Paul <[email protected]>
* gallium glsl: Fix crash with piglit ↵Maarten Lankhorst2014-04-171-1/+4
| | | | | | | | | | | | | | fs-deref-literal-array-of-structs.shader_test This allows the following shader code to work without a weird crash: struct Foo { int value[1]; }; int actual_value = Foo[2](Foo(int[1](100)), Foo(int[1](200)))[i].value[0]; Signed-off-by: Maarten Lankhorst <[email protected]>
* nouveau/vdec: small fixes to h264 handlingMaarten Lankhorst2014-04-174-24/+24
| | | | | | | | | | | nouveau_vp3_inter_sizes requires sliec_count as argument just as the other places that call it from h264 code do. Hopefully fixes something. Fix the status_vp code to allow status == 0 too, when processing hasn't started yet. set h264->second_field correctly.
* st/xa: Cache render target surfaceThomas Hellstrom2014-04-171-3/+15
| | | | | | | | | | | | | | | | Otherwise it will trick the gallium driver into thinking that the render target has actually changed (due to different pipe_surface pointing to same underlying pipe_resource). This is really badness for tiling GPUs like adreno. This also appears to fix a rendering error with Motif on vmwgfx. Why that is is still under investigation. Based on an idea by Rob Clark. Cc: "10.0 10.1" <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* st/xa: scissor to help tilersRob Clark2014-04-174-0/+48
| | | | | | | | | | | | | | Keep track of the maximal bounds of all the operations and set scissor accordingly. For tiling GPU's this can be a big win by reducing the memory bandwidth spent moving pixels from system memory to tile buffer and back. You could imagine being more sophisticated and splitting up disjoint operations. But this simplistic approach is good enough for the common cases. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
* st/xa: remove unneeded argsRob Clark2014-04-175-12/+8
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
* glsl: Small optimization for constant conditionalsIago Toral Quiroga2014-04-161-8/+2
| | | | | | | | Once the relevant branch has been identified do not iterate over the instructions in the branch, do a linked list insertion instead to avoid the loop. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Fix incorrect indentation.Iago Toral Quiroga2014-04-161-793/+782
| | | | Acked-by: Kenneth Graunke <[email protected]>
* meta: Clip src/dest rects in BlitFramebuffer, using the scissorChris Forbes2014-04-172-2/+43
| | | | | | | | | | | | | | | | | Fixes piglit's fbo-blit-stretch test on drivers which use the meta path. (i965: should fix Broadwell, but also fixes Sandybridge/Ivybridge/Haswell since this test falls off the blorp path now due to format conversion) V2: Use scissor instead of just mangling the rects, to avoid texcoord rounding problems. (Thanks Marek) V3: Rebase on Eric's CTSI meta changes; re-add _mesa_update_state in the CTSI path so that _mesa_clip_blit sees the correct bounds. Signed-off-by: Chris Forbes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77414 Reviewed-by: Anuj Phogat <[email protected]> Tested-by: Anuj Phogat <[email protected]>
* mesa: fix check for dummy renderbuffer in _mesa_FramebufferRenderbufferEXT()Samuel Iglesias Gonsalvez2014-04-161-2/+1
| | | | | | | | | | | | | | | | | | | | According to the spec: <renderbuffertarget> must be RENDERBUFFER and <renderbuffer> should be set to the name of the renderbuffer object to be attached to the framebuffer. <renderbuffer> must be either zero or the name of an existing renderbuffer object of type <renderbuffertarget>, otherwise an INVALID_OPERATION error is generated. This patch changes the previous returned GL_INVALID_VALUE to GL_INVALID_OPERATION. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76894 Cc: [email protected] Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]>
* i965: Don't make instructions with a null dest a barrier to scheduling.Matt Turner2014-04-161-4/+8
| | | | | | | | | | | | | | | | Now that we properly track accumulator dependencies, the scheduler is able to schedule instructions between the mach and mov in the common the integer multiplication pattern: mul acc0, x, y mach null, x, y mov dest, acc0 Since a null destination implies no dependency on the destination, we can also safely schedule instructions (that don't write the accumulator) between the mul and mach. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Change fs_visitor::emit_lrp to use MAC for gen<6Juha-Pekka Heikkila2014-04-161-7/+4
| | | | | | | | | This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD, saving one instruction and two temporary registers. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965/fs: Add support for the MAC instruction.Juha-Pekka Heikkila2014-04-162-0/+4
| | | | | | | | | | This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6Juha-Pekka Heikkila2014-04-161-16/+6
| | | | | | | | | This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD, saving one instruction and two temporary registers. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965/vec4: Add support for the MAC instruction.Juha-Pekka Heikkila2014-04-163-0/+5
| | | | | | | | | | This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
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