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* i965: Only do depth resolves prior to clearing when neededJason Ekstrand2017-07-261-3/+36
* i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.Kenneth Graunke2017-07-262-5/+8
* ac/surface: fix hybrid graphics where APU=GFX9, dGPU=olderMarek Olšák2017-07-261-0/+12
* radeonsi: decrease the number of compiler threadsMarek Olšák2017-07-262-3/+8
* gallium/radeon: make S_FIXED function signed and move it to shared codeMarek Olšák2017-07-263-9/+5
* st/mesa: also clamp and quantize per-unit lod biasMarek Olšák2017-07-263-4/+6
* st/mesa: fix unconditional return in st_framebuffer_iface_removeMarek Olšák2017-07-261-1/+1
* drirc: whitelist glthread for Mount and Blade WarbandMarek Olšák2017-07-261-0/+3
* egl: move KHR_no_error vs debug/robustness check further downGrigori Goronzy2017-07-261-11/+10
* radv: rename physical_device->uuid[] to cache_uuid[]Andres Rodriguez2017-07-263-5/+5
* radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+Nicolai Hähnle2017-07-261-15/+24
* radeonsi: fix detection of DRAW_INDIRECT_MULTI on SINicolai Hähnle2017-07-261-2/+2
* anv: only expose up to 28 vertex attributesIago Toral Quiroga2017-07-261-1/+1
* anv/cmd_buffer: fix off by one error in assertionIago Toral Quiroga2017-07-261-1/+1
* i965: Shut up Coverity warning about HiZ buffers.Kenneth Graunke2017-07-251-0/+1
* i965: Fix = vs == in MCS aux usage assert.Kenneth Graunke2017-07-251-1/+1
* i965: Fix offset addition in get_isl_surf.Kenneth Graunke2017-07-251-3/+3
* mesa/st: fix inconsistent indentation of st_cb_bufferobjects.cAndres Rodriguez2017-07-261-18/+18
* compiler: move glsl_interface_packing enum to shader_enums.hTimothy Arceri2017-07-264-27/+11
* mesa/st: fix unused variable warningsTimothy Arceri2017-07-264-10/+11
* mesa/st: move st_pipe_format_to_mesa_format() call to where its usedTimothy Arceri2017-07-261-2/+1
* gallium/util: fix unused variable warningTimothy Arceri2017-07-261-3/+5
* mesa: drop useless assertTimothy Arceri2017-07-261-1/+0
* mesa: call binding functions directly from glDeleteBuffersTimothy Arceri2017-07-261-3/+9
* mesa: move static binding functions above _mesa_DeleteBuffers()Timothy Arceri2017-07-261-207/+205
* mesa: don't try to re-generate the default bufferTimothy Arceri2017-07-261-6/+6
* broadcom/vc4: Switch the V3D 2.1 XML over to restricted address fields.Eric Anholt2017-07-251-4/+4
* broadcom/genxml: Support address fields with <32 bitsEric Anholt2017-07-251-1/+1
* broadcom/vc4: Use the RA callback to improve register selection's choices.Eric Anholt2017-07-251-1/+52
* ra: Add a callback for selecting a register from what's available.Eric Anholt2017-07-252-14/+82
* ra: Don't put a node in its own adjacency set.Eric Anholt2017-07-251-13/+10
* ra: Pull the body of a loop out to a helper function.Eric Anholt2017-07-251-12/+19
* broadcom/vc4: Scissor blits performed using the rendering engine.Eric Anholt2017-07-251-0/+9
* broadcom/vc4: Prefer blit via rendering to the software fallback.Eric Anholt2017-07-251-6/+8
* broadcom/vc4: Switch the Viewport Center fields to a fixed-point representation.Eric Anholt2017-07-252-4/+4
* broadcom/vc4: Use the XML decoder for CL dumping.Eric Anholt2017-07-253-443/+32
* broadcom/genxml: Introduce a V3D packet/struct decoder.Eric Anholt2017-07-259-0/+1066
* broadcom: add editorconfigEric Anholt2017-07-251-0/+3
* intel/decoder: Reuse the gen_make_gen() helper.Eric Anholt2017-07-251-3/+1
* intel/decoder: Reuse the MAX2 macro instead of defining another one.Eric Anholt2017-07-251-3/+1
* svga: implement MSAA alpha_to_one featureBrian Paul2017-07-255-1/+57
* svga: rework the FS white fragments codeBrian Paul2017-07-252-33/+21
* gallium/util: s/unsigned/enum tgsi_texture_type/Brian Paul2017-07-254-21/+24
* drirc: whitelist glthread for Overlord 1+2, Oil Rush, War Thunder, Saints Row 2Kamil Páral2017-07-251-2/+17
* i965: perf: flush batchbuffers at the beginning of queriesLionel Landwerlin2017-07-251-8/+8
* st/dri2: Return invalid modifier when no driver supportDaniel Stone2017-07-251-0/+6
* st/dri: Check get-handle return value in queryImageDaniel Stone2017-07-251-12/+18
* r600: Add support for B5G5R5A1.Michal Srb2017-07-251-0/+6
* radeon/vcn: move message buffer to vram for nowLeo Liu2017-07-251-1/+2
* trace: Correct transfer box size calculation.Jose Fonseca2017-07-251-9/+8
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