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* i965/vec4: Generate URB writes using a loop.Paul Berry2013-09-161-31/+21
| | | | | | | | | Previously we only ever did 1 or 2 URB writes, since the maximum number of varyings we support is small enough to fit in 2 URB writes. But GL 3.2 requires the geometry shader to support 128 output varying components, and this could require up to 3 URB writes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: When >64 input components, order them to match prev pipeline stage.Paul Berry2013-09-162-7/+45
| | | | | | | | | | | | | Since the SF/SBE stage is only capable of performing arbitrary reorderings of 16 varying slots, we can't arrange the fragment shader inputs in an arbitrary order if there are more than 16 input varying slots in use. We need to make sure that slots 16-31 match the corresponding outputs of the previous pipeline stage. The easiest way to accomplish this is to just make all varying slots match up with the previous pipeline stage. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Simplify computation of key.input_slots_valid during precompile.Paul Berry2013-09-161-11/+1
| | | | | | | | | | | The for loop was rather silly. In addition to checking brw->gen < 6 on each loop iteration, it took pains to exclude bits from fp->Base.InputsRead that don't correspond to fragment shader inputs. But those bits would never have been set in the first place, since the only bits that are ever set in fp->Base.InputsRead are fragment shader inputs. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Stop storing an input VUE map in the GS program key.Paul Berry2013-09-163-5/+8
| | | | | | | | | | | | | Now that the vertex shader output VUE map is determined solely by a 64-bit bitfield, we don't have to store it in its entirety in the geometry shader program key; instead, we can just store the bitfield, and let the geometry shader infer the VUE map at compile time. This dramatically reduces the size of the geometry shader program key, which we want to keep small since it gets recomputed whenever the active program changes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Remove VUE map dependency on userclip_active.Paul Berry2013-09-163-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | Previously, on Gen6+, we laid out the vertex (or geometry) shader VUE map differently depending whether user clipping was active. If it was active, we put the clip distances in slots 2 and 3 (where the clipper expects them); if it was inactive, we assigned them in the order of the gl_varying_slot enum. This made for unnecessary recompiles, since turning clipping on/off for a shader that used gl_ClipDistance might rearrange the varyings. It also required extra bookkeeping, since it required the user clipping flag to be provided to brw_compute_vue_map() as a parameter. With this patch, we always put clip distances at in slots 2 and 3 if they are written to. do_vs_prog() and do_gs_prog() are responsible for ensuring that clip distances are written to when user clipping is enabled (as do_vs_prog() previously did for gen4-5). This makes the only input to brw_compute_vue_map() a bitfield of which varyings the shader writes to, a fact that we'll take advantage of in forthcoming patches. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Stop wasting input attribute space on gl_FragCoord and gl_FrontFacing.Paul Berry2013-09-163-9/+11
| | | | | | | | | | | | | | | | | | Previously, if a fragment shader accessed gl_FragCoord or gl_FrontFacing, we would assign them their own slots in the fragment shader input attribute array, using up space that could be made available to real varyings. This was not strictly necessary (since these values are not true varyings, and are instead computed from other data available in the FS payload). But we had to do it anyway because the SF/SBE setup code assumed that every 1 bit in the gl_program::InputsRead bitfield corresponded to a genuine varying variable. Now that the SF/SBE code consults brw_wm_prog_data and only sets up the attributes that the fragment shader actually needs, we don't have to do this anymore. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sf: Consult brw_wm_prog_data when setting up SF/SBE state.Paul Berry2013-09-162-23/+35
| | | | | | | | | | | | | | | | | | | | Previously, the SF/SBE setup code delivered varying inputs to the FS in the order in which they appear in the gl_program::InputsRead bitfield, since that's what the FS expects. When we add support for more than 64 varying components, this will no longer always be the case, because the Gen6+ SF/SBE stage is only capable of performing arbitrary reorderings of 16 varying slots. So, when there are more than 16 vec4's worth of varying inputs, the FS will have to adjust the order its input varyings in order to partially match the order of outputs from the geometry or vertex shader. To allow extra flexibility in the ordering of FS varyings, this patch causes the SF/SBE to deliver varying inputs to the FS in exactly the order that the FS requests, by consulting brw_wm_prog_data::urb_setup and brw_wm_prog_data::num_varying_inputs. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sf: Consolidate common code for setting up gen6-7 attribute overrides.Paul Berry2013-09-163-129/+97
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sf: Use BRW_SF_URB_ENTRY_READ_OFFSET rather than hardcoded values.Paul Berry2013-09-164-4/+12
| | | | | | | | | We always program the SF unit to start reading the vertex URB entry at offset 1. In upcoming patches, we'll be adding FS code that relies on this. So consistently use the constant BRW_SF_URB_ENTRY_READ_OFFSET rather than hardcoding a 1. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Consult brw_wm_prog_data::num_varying_inputs when setting up WM state.Paul Berry2013-09-162-3/+5
| | | | | | | | | | | | | | | | | | | | | | | Previously, we assumed that the number of varying inputs consumed by the fragment shader was equal to the number of bits set in gl_program::InputsRead. However, we'll soon be making two changes that will cause that not to be true: - We'll stop wasting varying input space for gl_FragCoord and gl_FrontFacing, which aren't varyings. - For fragment shaders that have more than 16 varying inputs, we'll adjust the layout of the inputs to account for the fact that the SF/SBE pipeline stage can't reorder inputs beyond the first 16; if there are GS outputs that the FS doens't use (or vice versa) this may cause the number of FS varying inputs to change. So, instead of trying to guess the number of FS inputs from gl_program::InputsRead, simply read it from brw_wm_prog_data:num_varying_inputs, which is guaranteed to be correct since it's populated by fs_visitor::calculate_urb_setup(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Change brw_wm_prog_data::urb_read_length to num_varying_inputs.Paul Berry2013-09-163-5/+7
| | | | | | | | | | | | | | | | | | On gen4-5, the FS stage reads varying inputs from URB entries that were output by the SF thread, where each register stores the interpolation setup for two components of a vec4, therefore the FS urb_read_length is twice the number of FS input varyings. On gen6+, varying inputs are directly deposited in the FS payload by the SF/SBE fixed function logic, so urb_read_length is irrelevant. However, in future patches, it will be nice to be able to consult brw_wm_prog_data to determine how many varying inputs the FS expects (rather than inferring it from gl_program::InputsRead). So instead of storing urb_read_length, we simply store num_varying_inputs in brw_wm_prog_data. On gen4-5, we multiply this by 2 to recover the URB read length. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Expose "urb_setup" as part of brw_wm_prog_data.Paul Berry2013-09-164-8/+14
| | | | | | | | | | | | | | | | At the moment, for Gen6+, the FS assumes that all varying inputs are delivered to it in the order in which they appear in the gl_program::InputsRead bitfield, and the SF/SBE setup code ensures that they are delivered in this order. When we add support for more than 64 varying components, this will no longer always be possible, because the Gen6+ SF/SBE stage is only capable of performing arbitrary reorderings of 16 varying slots. To allow extra flexibility in the ordering of FS varyings, this patch causes the FS to advertise exactly what ordering it expects. Reviewed-by: Kenneth Graunke <[email protected]>
* ilo: make ilo_bind_sampler_states return voidChia-I Wu2013-09-171-16/+25
| | | | | So that it can be hooked up pipe_context::bind_sampler_states that is currently living on another branch.
* glsl/tests: Update .gitignore for new unit test.Kenneth Graunke2013-09-161-0/+1
| | | | | | I rarely run 'git status', so I failed to notice this was missing. Signed-off-by: Kenneth Graunke <[email protected]>
* glsl/tests: Add a test for properties of sampler types.Kenneth Graunke2013-09-152-0/+114
| | | | | | | | | | | | For each sampler type, this tests that: - The base type is GLSL_TYPE_SAMPLER. - The dimensionality is set correctly. - The returned data type is correct. - The sampler_array and sampler_shadow flags are set correctly. - sampler_coordinate_components() returns the correct value. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: don't dereference stObj->pt if NULLDave Airlie2013-09-161-1/+1
| | | | | | | | | | | It seems a user app can get us into this state, I trigger the fail running fbo-maxsize inside virgl, it fails to create the backing storage for the texture object, but then segfaults here when it should fail the completeness test. Cc: "9.2" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nouveau: fix regression since float comparison instructions (v2)Dave Airlie2013-09-166-14/+14
| | | | | | | | | | Fix the return type and allow src and dst types for comparison to be separate, this at least fixes the two test cases I've written. v2: drop the u32->s32 change Acked-by: Christoph Bumiller <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vdpau/decode: Check max width and max height.Rico Schüller2013-09-151-0/+20
| | | | Reviewed-by: Christian König <[email protected]>
* freedreno: PIPE_TRANSFER_DISCARD_WHOLE_RESOURCERob Clark2013-09-141-17/+43
| | | | | | | When the old contents do not need to be preserved, it is faster to create a new backing bo rather than stall. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix VFD_INDEX_MAX overflowRob Clark2013-09-141-1/+1
| | | | | | | max_index may be 0xffffffff. The hardware does not need 1 + max_index (although it does not hurt unless max_index wraps around to zero). Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug option to disable GMEM bypassRob Clark2013-09-143-1/+3
| | | | | | Useful for debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle front_ccwRob Clark2013-09-145-17/+14
| | | | | | Used by supertuxkart. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: stencil fixesRob Clark2013-09-149-7/+30
| | | | | | | | For mem->gmem we don't sample depth/stencil as it's native type. So we need to setup the swizzle state for the sampler based on the format used for sampling. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: alpha-testRob Clark2013-09-147-7/+29
| | | | | | | Needed by some games, like etuxracer and supertuxkart which use alpha test rather than blending, to handle texture transparency. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: implement SUBRob Clark2013-09-141-3/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: use INDIRECT state load for shadersRob Clark2013-09-143-8/+29
| | | | | | | | | With a debug option to force DIRECT (mainly to make it easier for capturing cmdstream dumps). Using INDIRECT for large shaders at least makes a noticable reduction in CPU load, which helps for CPU limited games. Signed-off-by: Rob Clark <[email protected]>
* freedreno: avoid stalling at ringbuffer wraparoundRob Clark2013-09-142-22/+41
| | | | | | | | | Because of how the tiling works, we can't really flush at arbitrary points very easily. So wraparound is handled by resetting to top of ringbuffer. Previously this would stall until current rendering is complete. Instead cycle through multiple ringbuffers to avoid a stall. Signed-off-by: Rob Clark <[email protected]>
* freedreno: emit markers to scratch registersRob Clark2013-09-144-0/+33
| | | | | | | | | Emit markers by writing to scratch registers in order to "triangulate" gpu lockup position from post-mortem register dump. By comparing register values in post-mortem dump to command-stream, it is possible to narrow down which DRAW_INDX caused the lockup. Signed-off-by: Rob Clark <[email protected]>
* freedreno: split out WFI helperRob Clark2013-09-145-10/+12
| | | | | | Mostly just to give an easy debug/instrumentation point. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fd_draw helperRob Clark2013-09-146-52/+55
| | | | | | | Have a single helper that all draws come through.. mainly for a convenient debug and instrumentation point. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix gpu lockup in some piglit testsRob Clark2013-09-141-1/+1
| | | | | | | | | The varying-out config comes from the inputs of the frag shader (so that we aren't exporting unneeded varyinges). The varyings-count should come from the frag shader as well, to avoid a discrepency in configuration and resulting gpu lockup. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: add LITRob Clark2013-09-141-3/+142
| | | | | | Needed by glxgears and etuxracer ;-) Signed-off-by: Rob Clark <[email protected]>
* freedreno: multi-slice resources (cubemap, mipmap, etc)Rob Clark2013-09-1415-52/+141
| | | | Signed-off-by: Rob Clark <[email protected]>
* glsl/builtins: Fix {texture1D,texture2D,shadow1D}ArrayLod availibility.Paul Berry2013-09-131-5/+5
| | | | | | | | | | | | | | These functions are defined in EXT_texture_array, which makes no mention of what shader types they should be allowed in. At the time EXT_texture_array was introduced, functions ending in "Lod" were available only in vertex shaders, however this restriction was lifted in later spec versions and extensions. We already have the function lod_exists_in_stage() for figuring out whether functions ending in "Lod" should be available, so just re-use that. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use brw_stage_state for WM data as well.Kenneth Graunke2013-09-1313-93/+71
| | | | | | | | This gets the VS, GS, and PS all using the same data structure. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Increase the size of brw_stage_state::surf_offset.Kenneth Graunke2013-09-131-1/+1
| | | | | | | | | | Since BRW_MAX_WM_SURFACES is greater than BRW_MAX_VEC4_SURFACES, the existing array isn't large enough to be used by the WM. Increasing it will make it possible to share them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add comments to the new brw_state_state structure's fields.Kenneth Graunke2013-09-131-0/+10
| | | | | | | | | | These are largely based on the similar fields in brw->wm. v2: Add a better comment than "Scratch buffer". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* mesa: Rename MESA_shader_integer_mix to EXT_shader_integer_mixIan Romanick2013-09-137-9/+9
| | | | | | | | | | | | | | Everyone at the Khronos meeting was as surprised that GLSL didn't already support this as we were. Several vendors said they'd ship it, but there didn't seem to be enough interest to put in the effort to make it ARB or KHR. v2: Fix a couple typos and rename the spec file to EXT_shader_integer_mix.spec. Suggested by Roland. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: fix and enable transform feedback for CIKMarek Olšák2013-09-134-28/+40
| | | | | | The CP_STRMOUT_CNTL register was moved again. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix gl_InstanceID with non-zero start_instanceMarek Olšák2013-09-131-3/+4
| | | | | | | | start_instance doesn't affect gl_InstanceID. There's no piglit test, but it's kinda obvious the code was wrong. Reviewed-by: Christian König <[email protected]>
* gallium: comment that INSTANCEID doesn't include start_instanceMarek Olšák2013-09-131-1/+1
| | | | Reviewed-by: Christian König <[email protected]>
* radeonsi: enable streamout AKA transform feedback for SIMarek Olšák2013-09-131-10/+4
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement streamout shader supportMarek Olšák2013-09-133-15/+276
| | | | | | | | | | | The shader is responsible for writing to streamout buffers using the TBUFFER_STORE_FORMAT_* instructions. The locations of some input SGPRs and VGPRs are assigned dynamically, because the input SGPRs controlling streamout are not declared if they are not needed, decreasing the indices of all following inputs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement glDrawTransformFeedback functionalityMarek Olšák2013-09-133-0/+30
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix streamout queriesMarek Olšák2013-09-131-4/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: implement streamout flush properlyMarek Olšák2013-09-131-1/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: bind streamout buffers to VGT and the vertex shaderMarek Olšák2013-09-134-8/+81
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: handle rasterizer_discard and set GS_OUT_PRIM_TYPEMarek Olšák2013-09-133-1/+31
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: initialize the first CS like any otherMarek Olšák2013-09-135-5/+15
| | | | | | | | | So that the "init" state is always emitted first and not later in draw_vbo. This fixes streamout where the "init" state, which disables streamout, was emitted in draw_vbo after streamout was enabled. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: integrate shared streamout stateMarek Olšák2013-09-137-38/+20
| | | | Reviewed-by: Michel Dänzer <[email protected]>
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