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* gallium/util: get h264 level based on number of max references and resolutionLeo Liu2015-04-281-0/+36
| | | | | | | | v2: add commments for limitation of max references numbers, and what the caculation is based Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* r600g,radeonsi: add a driver query returning GPU loadMarek Olšák2015-04-288-2/+194
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g,radeonsi: add driver queries for GPU temperature and shader+memory clocksMarek Olšák2015-04-285-3/+58
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gm107/ir: add lane/vertex count sysvalsIlia Mirkin2015-04-271-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: add support for writing per-patch and shader outputsIlia Mirkin2015-04-271-7/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: color masking works like a blend for some formatsIlia Mirkin2015-04-271-0/+14
| | | | | | | | When there is a colormask active that does not cover all the channels, enable reading in the destination like with a combining blend operation. This fixes fbo-blending-formats on a3xx. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for S8 and Z32F_S8Ilia Mirkin2015-04-279-44/+235
| | | | | | | | | Enables ARB_depth_buffer_float. There is no sampling support for interleaved Z32F_S8, so we store the two textures separately, one as Z32F, the other as S8. As a result, we need a lot of additional logic for restores and transfers. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add Z32F supportIlia Mirkin2015-04-275-10/+65
| | | | | | | | | 32-bit depth buffers are stored as unorm, and thus need special handling when moving to and from gmem. They are copied into gmem by writing depth, and resolved from gmem using a special resolve bit which apparently float-ifies the data. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: add fd_transfer to wrap around pipe_transferIlia Mirkin2015-04-273-2/+15
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for disabling depth clippingIlia Mirkin2015-04-272-1/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* i965/vs: Remove unnecessary NULL check on generate_code() result.Kenneth Graunke2015-04-271-2/+1
| | | | | | | | | Code generation is not allowed to fail for any reason - in fact, fs_generator has no mechanism for failing. The visitor is responsible for that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: fix packing support for arrays of doublesTimothy Arceri2015-04-281-2/+2
| | | | | | | Broke in commit f00c5f85b82efe9535b18dbf97c4591fb28aeae6 when adding support for multidimensional arrays Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
* i965: Enable ARB_gpu_shader5 on Gen8+.Matt Turner2015-04-271-6/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix code emission for imul_high in NIR.Matt Turner2015-04-271-1/+23
| | | | | | Copy over from brw_fs_visitor.cpp. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix stride for multiply in macro.Matt Turner2015-04-271-0/+2
| | | | | | | | We have to use W/UW type for src1 of the multiply in the MUL/MACH macro, but in order to read the low 16-bits of each 32-bit integer, we need to set the appropriate stride. Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965/fs: Allow SIMD16 borrow/carry/64-bit multiply on Gen > 7."Matt Turner2015-04-271-3/+3
| | | | | | | | | This reverts commit 9f5e5bd34d8ba48c851b442fb88f742b1ba6a571. I have no idea what made me believe these didn't apply to Gen > 7. They do, and without them we generate bad code that causes failures on Gen 8. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix up GLSL version when computing GL versionIlia Mirkin2015-04-271-0/+17
| | | | | | | | | | | In some situations it is convenient for a driver to expose a higher GLSL version while some extensions are still incomplete. However in that situation, it would report a GLSL version that was higher than the GL version. Avoid that situation by limiting the GLSL version to the GL version. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* softpipe: fix another stencil-as-float issueRoland Scheidegger2015-04-271-2/+2
| | | | | | | | | Hopefully this is the last one now (for texture X32_S8X24_UINT views). +4 piglits. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90167 Reviewed-by: Brian Paul <[email protected]>
* mesa: the function name appears to have a gl prefix alreadyIlia Mirkin2015-04-271-2/+2
| | | | | | | | | | | | Currently we're producing errors like User error: GL_INVALID_OPERATION in glglDeleteProgramsARB(invalid call) And noop_warn appears to be called with the full function name. Don't prepend a gl prefix. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* Fix a few typosZoë Blade2015-04-2772-95/+95
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* i965/gen8: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-271-60/+77
| | | | | | | gen8_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965/gen7: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-272-54/+84
| | | | | | | gen7_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965: Add helper functions to calculate the slice pitch of an array or 3D ↵Francisco Jerez2015-04-272-40/+84
| | | | miptree.
* scons: add target osmesa using gallium state tracker.Olivier Pena2015-04-277-1/+110
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* radeonsi: set an optimal value for DB_Z_INFO.ZRANGE_PRECISIONMarek Olšák2015-04-271-7/+2
| | | | | | Required because of a VI hw bug. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove deprecated and useless registersMarek Olšák2015-04-271-10/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove useless includesMarek Olšák2015-04-271-3/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: print winsys info with R600_DEBUG=infoMarek Olšák2015-04-272-0/+28
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: make radeon_bo_vtbl staticMarek Olšák2015-04-271-2/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* glsl: replace while loop with without_array functionTimothy Arceri2015-04-271-3/+1
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: support packing of arrays of arraysTimothy Arceri2015-04-271-8/+2
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: add arrays of arrays support to without_array functionTimothy Arceri2015-04-271-1/+6
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/hud: add more options to customize HUD panesGediminas Jakutis2015-04-262-6/+161
| | | | | | | | | | | | | | | | Extends the syntax of GALLIUM_HUD environment variable to: - Add options to set the size and exact location of each pane. - Add an option to limit the maximum allowed value of the X axis on a pane, clamping the graph down to not go above this value. - Add an option to auto-adjust the value of the Y axis down to the highest value still visible on the graph. v2: - Make the patch simpler and smaller. - With dynamic auto-adjusting on, adjust the Y axis once per pane update instead of updating once every several seconds. - No longer mishandle pane height when having more than one graph per pane.
* i965: Fill out the rest of brw_debug_recompile_sampler_key().Kenneth Graunke2015-04-251-0/+8
| | | | | | | | | | This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs. UMS/IMS differences and Sandybridge textureGather workarounds. Previously, we just flagged them as "Something else". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Disassemble sampler message names on Gen5+.Kenneth Graunke2015-04-251-4/+34
| | | | | | | | | | | | | | | | | | | | | | Previously, sampler messages were decoded as sampler (1, 0, 2, 2) mlen 6 rlen 8 { align1 1H }; I don't know how much time we've collectly wasted trying to read this format. I can never recall which number is the surface index, sampler index, message type, or...whatever that other number is. Figuring out the message name from the numerical code is also painful. Now they decode as: sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; This is easy to read at a glance, and matches the format I used for render target formats. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Disallow constant propagation into POW on Gen 6.Matt Turner2015-04-251-2/+8
| | | | | Fixes assertion failures in three piglit tests on Gen 6 since commit 0087cf23e.
* mesa: add support for exposing up to GL4.2Ilia Mirkin2015-04-241-1/+45
| | | | | | | | | Add the 4.0/4.1/4.2 extensions lists to compute_version. A couple of extensions aren't in mesa yet, so those are marked with 0 until they become supported. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add missing pixel_x/y to brw_instruction_name().Matt Turner2015-04-241-0/+5
| | | | Forgotten in commit 529064f6.
* i965/fs: Don't constant propagate into integer math instructions.Matt Turner2015-04-242-3/+5
| | | | | | Constant combining won't promote non-floats, so this isn't safe. Fixes regressions since commit 0087cf23e.
* mesa: put more info in glTexImage GL_OUT_OF_MEMORY error messageBrian Paul2015-04-241-1/+3
| | | | | | | Give the user some idea about the size of the texture which caused the GL_OUT_OF_MEMORY error. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Allow 2-src math instructions to have immediate src1.Matt Turner2015-04-242-7/+11
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Transform pow(x, 4) into (x*x)*(x*x).Matt Turner2015-04-241-0/+1
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* glsl: Transform pow(x, 4) into (x*x)*(x*x).Matt Turner2015-04-241-0/+20
| | | | | Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix glGetActiveUniformsiv regressionTapani Pälli2015-04-241-4/+16
| | | | | | | | | | | Commit 7519ddb caused regression to glGetActiveUniformsiv. Patch adds back validation loop of all given uniforms before writing any values, not touching params in case of errors is tested by the conformance suite. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149 Reviewed-by: Martin Peres <[email protected]>
* mesa: refactor active attrib queries for glGetProgramivTapani Pälli2015-04-241-25/+14
| | | | | | | | | | | | | | | Main motivation here is to get rid of iterating IR and encapsulate queries within program resources. No functional changes. Piglit tests calling the modified functionality: - gl-get-active-attrib-returns-all-inputs - glsl-1.50-get-active-attrib-array - getactiveattrib Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* i965: Add an INTEL_DEBUG=spill option to test spillingJason Ekstrand2015-04-233-1/+3
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/debug: Use the ull specifier for DEBUG enum definesJason Ekstrand2015-04-231-31/+31
| | | | | | | The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer than 32 bits, you need to use ull. We might as well use it for all of them. Reviewed-by: Matt Turner <[email protected]>
* i965: Disallow linear blits that are not cacheline aligned.Kenneth Graunke2015-04-231-8/+19
| | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. The main user, intel_emit_linear_blit, now handles this properly. But we might also have linear miptrees; just refuse to blit those. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.Kenneth Graunke2015-04-231-8/+14
| | | | | | | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings. Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* mapi: Adding missing string.h include.Pali Rohár2015-04-231-0/+2
| | | | | | | | File glapi_entrypoint.c calls memcpy() function, but does not include string.h header. So compilation can fail at error: implicit declaration of function 'memcpy'. Signed-off-by: Jose Fonseca <[email protected]>
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