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* llvmpipe: s/Elements/ARRAY_SIZE/Brian Paul2016-04-2712-54/+54
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: s/Elements/ARRAY_SIZE/Brian Paul2016-04-276-28/+28
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* os: s/Elements/ARRAY_SIZE/Brian Paul2016-04-271-1/+1
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* hud: s/Elements/ARRAY_SIZE/Brian Paul2016-04-273-7/+7
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: s/Elements/ARRAY_SIZE/Brian Paul2016-04-279-29/+29
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* draw: s/Elements/ARRAY_SIZE/Brian Paul2016-04-277-24/+24
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: s/Elements/ARRAY_SIZE/Brian Paul2016-04-277-27/+27
| | | | | | | Try to standardize on the later, which is defined in the common util/ directory. Reviewed-by: Jose Fonseca <[email protected]>
* winsys/radeon: remove use_reusable_pool parameter from buffer_createNicolai Hähnle2016-04-2711-26/+17
| | | | | | All callers set this parameter to true. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: remove use_reusable_pool parameter from r600_init_resourceNicolai Hähnle2016-04-275-9/+7
| | | | | | All callers set it to true. Reviewed-by: Marek Olšák <[email protected]>
* radeon/video: always use the reusable buffer poolNicolai Hähnle2016-04-274-5/+5
| | | | | | | | | | | A semantic error was introduced in a past refactoring that caused the bind parameter to be passed into the use_reusable_pool parameter of buffer_create. Since this clearly makes no sense, and there is no clear reason why the cache _shouldn't_ be used, just use the cache always. Cc: Christian König <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: work around an MSAA fast stencil clear problemNicolai Hähnle2016-04-271-3/+15
| | | | | | | | A piglit test (arb_texture_multisample-stencil-clear) has been sent. This problem was discovered analyzing Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: expclear must be disabled on first Z/S clearNicolai Hähnle2016-04-271-2/+2
| | | | | | The documentation and the HW team say so. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move blend choice out of loop in si_blit_decompress_colorNicolai Hähnle2016-04-271-9/+9
| | | | | | It does not depend on the level or layer. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use level mask for early out in si_blit_decompress_colorNicolai Hähnle2016-04-271-6/+8
| | | | | | | | Mostly for consistency with the other decompress functions, but note that in the non-DCC decompress case, the function can now early-out in slightly more (albeit probably rare) cases. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: si_blit_decompress_depth is only used for stagingNicolai Hähnle2016-04-271-21/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: only decompress the required ZS planes from si_blitNicolai Hähnle2016-04-271-6/+7
| | | | | | | | | This happens to "fix" a rendering bug in KotOR2, because it avoids a still not quite understood bug with MSAA fast stencil clear decompress. For the stencil clear bug, I have sent a piglit test (arb_texture_multisample-stencil-clear). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: decompress Z & S planes in one passNicolai Hähnle2016-04-271-28/+73
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: early out of si_blit_decompress_depth_in_place based on dirty maskNicolai Hähnle2016-04-271-6/+14
| | | | | | Avoid dirtying the db_render_state atom when possible. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use MIN2 instead of expanded ?: operatorNicolai Hähnle2016-04-271-3/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix brace styleNicolai Hähnle2016-04-271-2/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: add u_bit_consecutive for generating a consecutive range of bitsNicolai Hähnle2016-04-271-0/+12
| | | | | | | There are some undefined behavior subtleties, so having a function to match the u_bit_scan_consecutive_range makes sense. Reviewed-by: Marek Olšák <[email protected]>
* swr: s/Elements/ARRAY_SIZE/Tim Rowley2016-04-273-7/+7
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: emit s_waitcnt for shader memory barriers and volatileNicolai Hähnle2016-04-271-13/+23
| | | | | | | | | Turns out that this is needed after all to satisfy some strengthened coherency tests. Depends on support in LLVM, added in r267729. v2: updated to reflect changes to the LLVM intrinsic Reviewed-by: Marek Olšák <[email protected]> (v1)
* swr: [rasterizer] warning cleanupTim Rowley2016-04-279-74/+27
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] implement legacy depth bias enableTim Rowley2016-04-274-21/+25
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] support for dumping x86 asmTim Rowley2016-04-272-0/+50
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] more backend refactoringTim Rowley2016-04-278-963/+573
| | | | | | | | | BackendPixelRate should be easier to read/maintain now hopefully. Small perf bump by moving some of the pfn's to inline functions without template params. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] add mSimdInt1TyTim Rowley2016-04-272-0/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] backend refactorTim Rowley2016-04-275-238/+633
| | | | | | | Lump all template args into a bundle of traits, and add some functionality to the MSAA traits. Reviewed-by: Bruce Cherniak <[email protected]>
* svga: use the SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS queryBrian Paul2016-04-271-0/+3
| | | | | | | | | | | Instead of a hard-coded 512. The query typically returns 65536 now. Fall back to 512 if the query fails as we do for vertex shaders (which should never happen). Note that we don't actually enforce this limit in our shaders but it gets reported via the glGetProgramivARB(GL_MAX_PROGRAM_INSTRUCTIONS_ARB) query. Reviewed-by: Charmaine Lee <[email protected]>
* nouveau: codegen: LOAD: Take src swizzle into accountHans de Goede2016-04-272-2/+9
| | | | | | | | | | | | | | | | | | | | | | The llvm TGSI backend uses pointers in registers and does things like: LOAD TEMP[0].y, MEMORY[0], TEMP[0] Expecting the data at address TEMP[0].x to get loaded to TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be loaded instead. This commit adds support for a swizzle suffix for the 1st source operand, which allows using: LOAD TEMP[0].y, MEMORY[0].xxxx, TEMP[0] And actually getting the desired behavior Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: codegen: LOAD: Do not call fetchSrc(1) if the address is immediateHans de Goede2016-04-271-2/+3
| | | | | | | | | | "off" later gets set to NULL when the address is immediate, so move the fetchSrc(1) call to the non-immediate branch of the if-else. This brings handleLOAD's offset handling inline with how it is done in handleSTORE. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: codegen: LOAD: Always use component 0 when getting the addressHans de Goede2016-04-271-1/+3
| | | | | | | | | | LOAD loads upto 4 components from the specified resource starting at the passed in x value of the 2nd source operand, the y, z and w components of the address should not be used. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* dri3: Check for dummyContext to see if the glx_context is validStefan Dirsch2016-04-271-6/+2
| | | | | | | | | | | | According to the comments in src/glx/glxcurrent.c __glXGetCurrentContext() always returns a valid pointer. If no context is made current, it will contain dummyContext. Thus a test for NULL will always fail. https://lists.freedesktop.org/archives/mesa-dev/2016-April/113962.html Signed-off-by: Stefan Dirsch <[email protected]> Reviewed-by: Egbert Eich <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* dri2: Check for dummyContext to see if the glx_context is validEgbert Eich2016-04-271-1/+1
| | | | | | | | | | | | According to the comments in src/glx/glxcurrent.c __glXGetCurrentContext() always returns a valid pointer. If no context is made current, it will contain dummyContext. Thus a test for NULL will always fail. https://bugzilla.opensuse.org/show_bug.cgi?id=962609 Tested-by: Olaf Hering <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl: move uniform block validation to link_uniform_blocks.cppTimothy Arceri2016-04-272-53/+53
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Enable ARB_texture_stencil8 and OES_texture_stencil8 on Gen8+.Kenneth Graunke2016-04-263-7/+2
| | | | | | | | | | | | | | | | | | | | | Stencil texturing is required by ES 3.1. Apparently we never actually turned it on. Do that now. Also turn on the desktop extension. Fixes nine dEQP-GLES31.functional tests: stencil_texturing.format.stencil_index8_2d texture.border_clamp.formats.stencil_index8.nearest_size_pot texture.border_clamp.formats.stencil_index8.nearest_size_npot texture.border_clamp.formats.stencil_index8.gather_size_pot texture.border_clamp.formats.stencil_index8.gather_size_npot texture.border_clamp.unused_channels.stencil_index8 state_query.internal_format.renderbuffer.stencil_index8_samples state_query.internal_format.texture_2d_multisample.stencil_index8_samples state_query.internal_format.texture_2d_multisample_array.stencil_index8_samples Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* mesa: Try to fix CopyTex[Sub]Image of stencil textures.Kenneth Graunke2016-04-261-2/+3
| | | | | | | | | | | | | ES prohibits this, but GL appears to allow it. We at least need this much, or else we'll crash as there's no source to read from. This fixed crashes in the ES tests before I realized I needed to prohibit stencil instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* mesa: Disallow CopyTexSubImage on stencil formats in ES.Kenneth Graunke2016-04-261-0/+9
| | | | | | | | | | | Fixes - ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8 - ES31-CTS.gtf.GL31Tests.texture_stencil8.texture_stencil8_multisample Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Fix MapTextureImage for multi-slice/level stencil buffers.Kenneth Graunke2016-04-261-2/+2
| | | | | | | | | | | We called intel_miptree_get_image_offset() to get the image offsets for the current level/slice, but then proceeded to ignore the results and clobber level/slice 0 every time. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94713 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Move TCS output indirect_offset.file check out a level.Kenneth Graunke2016-04-261-42/+46
| | | | | | | | I want to add another condition. Moving the indirect_offset.file check out a level should make this a little easier. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Reduce the response length of sampler messages on Skylake.Kenneth Graunke2016-04-264-5/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Often, we don't need a full 4 channels worth of data from the sampler. For example, depth comparisons and red textures only return one value. To handle this, the sampler message header contains a mask which can be used to disable channels, and reduce the message length (in SIMD16 mode on all hardware, and SIMD8 mode on Broadwell and later). We've never used it before, since it required setting up a message header. This meant trading a smaller response length for a larger message length and additional MOVs to set it up. However, Skylake introduces a terrific new feature: for headerless messages, you can simply reduce the response length, and it makes the implicit header contain an appropriate mask. So to read only RG, you would simply set the message length to 2 or 4 (SIMD8/16). This means we can finally take advantage of this at no cost. total instructions in shared programs: 9091831 -> 9073067 (-0.21%) instructions in affected programs: 191370 -> 172606 (-9.81%) helped: 2609 HURT: 0 total cycles in shared programs: 70868114 -> 68454752 (-3.41%) cycles in affected programs: 35841154 -> 33427792 (-6.73%) helped: 16357 HURT: 8188 total spills in shared programs: 3492 -> 1707 (-51.12%) spills in affected programs: 2749 -> 964 (-64.93%) helped: 74 HURT: 0 total fills in shared programs: 4266 -> 2647 (-37.95%) fills in affected programs: 3029 -> 1410 (-53.45%) helped: 74 HURT: 0 LOST: 1 GAINED: 143 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add a helper for figuring out what channels of an SSA def are readJason Ekstrand2016-04-262-0/+27
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Use inst->regs_written for rlen for texture instructionsJason Ekstrand2016-04-262-9/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Properly report regs_written from SAMPLEINFOJason Ekstrand2016-04-262-2/+9
| | | | | | | | | The previous behavior would only allocate one register and then write four thus potentially stomping three innocent bystanders. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Set regs_written on texturing instructionsJason Ekstrand2016-04-261-0/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Don't force a header for texture offsets of 0.Kenneth Graunke2016-04-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Calling textureOffset() with an offset of <0, 0, 0> is equivalent to calliing texture(). We don't actually need to set up an offset, which causes a message header to be created. A fairly common pattern is to sample at a point with a bunch of offsets, and average them. It's natural to write all the lookups as textureOffset, but use <0, 0> for the center sample. shader-db results on Skylake: total instructions in shared programs: 9092095 -> 9092087 (-0.00%) instructions in affected programs: 2826 -> 2818 (-0.28%) helped: 12 HURT: 2 total cycles in shared programs: 70870166 -> 70870144 (-0.00%) cycles in affected programs: 15924 -> 15902 (-0.14%) helped: 2 HURT: 0 This also helps prevent code quality regressions in a future patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by Jason Ekstrand <[email protected]>
* r600g: fix and optimize tgsi_cmp when using ABS and NEG modifierPatrick Rudolph2016-04-271-1/+10
| | | | | | | | | | | | | | Some apps set NEG and ABS on the source param to test for zero. Use ALU_OP3_CNDE insted of ALU_OP3_CNDGE and unset both modifiers. It also removes the need for a MOV instruction, as ABS isn't supported on op3. Tested on AMD CAYMAN and AMD RV770. Signed-off-by: Patrick Rudolph <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* softpipe: add support for compute shaders. (v2)Dave Airlie2016-04-278-3/+369
| | | | | | | | | | | | | | | | | This enables ARB_compute_shader on softpipe. I've only tested this with piglit so far, and I hopefully plan on integrating it with my vulkan work. I'll get to testing it with deqp more later. The basic premise is to create up to 1024 restartable TGSI machines, and execute workgroups of those machines. v1.1: free machines. v2: deqp fixes - add samplers support, finish atomic operations, fix load/store writemasks. Acked-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi/exec: initialise SysSemanticToIndex array to -1Dave Airlie2016-04-271-0/+3
| | | | | | | | We want to use the SysSemanticToIndex to tell if we've seen the semantics at all. Acked-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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