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* etnaviv: replace translate_clear_color with util_pack_colorLucas Stach2017-06-162-48/+12
* etnaviv: remove bogus assertLucas Stach2017-06-161-2/+0
* etnaviv: use padded width/height for resource copiesLucas Stach2017-06-161-2/+2
* etnaviv: don't try RS blit if blit region is unalignedLucas Stach2017-06-161-1/+2
* Revert "amd/common: add missing libdrm include path"Emil Velikov2017-06-161-1/+0
* ac: remove amdgpu.h dependencyEmil Velikov2017-06-162-2/+6
* r600g,compute: provide local copy of functions from ac_binary.cJan Vesely2017-06-167-46/+199
* r600: android: amdgpu_common is only required when building OpenCLJan Vesely2017-06-161-5/+0
* egl/display: make platform detection thread-safeEric Engestrom2017-06-161-7/+12
* egl/display: only detect the platform onceEric Engestrom2017-06-161-14/+17
* svga: Relax the format checks for copy_region_vgpu10 somewhatThomas Hellstrom2017-06-161-2/+26
* svga: Fix incorrect format conversion blit destinationThomas Hellstrom2017-06-161-1/+3
* svga: Fix srgb copy_region regressionThomas Hellstrom2017-06-161-1/+4
* svga: Prefer accelerated blits over cpu copy regionThomas Hellstrom2017-06-161-5/+3
* svga: Support accelerated conditional blittingThomas Hellstrom2017-06-164-43/+62
* svga: Use utility functions to help determine whether we can use copy_regionThomas Hellstrom2017-06-161-6/+3
* svga: Rework the blit and resource_copy_region functionality v3Thomas Hellstrom2017-06-161-201/+445
* i965: Improve conditional rendering in fallback paths.Kenneth Graunke2017-06-153-47/+48
* mesa: stop assigning unused storage for non-bindless opaque typesTimothy Arceri2017-06-161-36/+6
* egl/android: Fix typ-oRobert Foss2017-06-151-1/+1
* draw: check for line_width != 1.0f in validate_pipeline()Brian Paul2017-06-151-3/+4
* svga: clamp device line width to at least 1 to fix HWv8 line stipplingBrian Paul2017-06-151-4/+4
* draw: whitespace and formatting fixesBrian Paul2017-06-152-60/+58
* automake: increase the MESA_GIT_SHA1 hash id length from 7 to 10 digitsBrian Paul2017-06-151-2/+2
* gallium: Add renderonly-based support for pl111+vc4.Eric Anholt2017-06-1522-4/+320
* etnaviv: Only use renderonly_get_handle for GEM handles.Eric Anholt2017-06-152-1/+3
* android: r600/eg: add support for tracing IBs after a hang.Mauro Rossi2017-06-151-0/+10
* svga: fix git_sha1.h include path in Android.mk (v3)Mauro Rossi2017-06-156-14/+66
* gallium/radeon: fix initialization of new resource bindless fieldsSamuel Pitoiset2017-06-151-0/+2
* gbm: implement FD import with modifierLucas Stach2017-06-151-0/+54
* gbm: add API to to import FD with modifierLucas Stach2017-06-151-0/+12
* i965: gen4_blorp_exec.h to the sources listEmil Velikov2017-06-152-1/+1
* gallium/util: Break recursion in pipe_resource_referenceMichel Dänzer2017-06-151-2/+8
* mesa: fix 'make check' by moving bindless functions at the right placeSamuel Pitoiset2017-06-151-18/+18
* i965/miptree: Use the new simple alloc_tiled for CCS buffersJason Ekstrand2017-06-141-7/+2
* i965/bufmgr: Add a new, simpler, bo_alloc_tiledJason Ekstrand2017-06-142-0/+26
* i965/bufmgr: Rename bo_alloc_tiled to bo_alloc_tiled_2dJason Ekstrand2017-06-144-44/+44
* i965: Use blorp for depth/stencil clears on gen6+Jason Ekstrand2017-06-143-0/+115
* i965: Set step_rate = 0 for interleaved vertex buffersJason Ekstrand2017-06-141-0/+1
* i965: Disable the interleaved vertex optimization when instancingJason Ekstrand2017-06-141-5/+6
* intel/blorp: Work around Sandy Bridge occlusion query issueJason Ekstrand2017-06-141-0/+10
* i965/blorp: Set no_depth_or_stencil correctlyJason Ekstrand2017-06-141-1/+2
* i965: Remove some unneeded fields from brw_contextJason Ekstrand2017-06-141-12/+0
* i965: Remove some of the remnants of metaJason Ekstrand2017-06-143-3/+2
* intel/isl: Properly set SeparateStencilBufferEnable on gen5-6Jason Ekstrand2017-06-141-3/+10
* i965/miptree: Choose the stencil layout in miptree_create_layoutJason Ekstrand2017-06-141-2/+4
* mesa: Add a BUFFER_BITS mask for depth+stencilJason Ekstrand2017-06-141-0/+3
* i965/blorp: Set aux_usage to NONE for miplevels without HiZJason Ekstrand2017-06-141-0/+6
* radeon/winsys: Limit max allocation size to 70% of VRAMAaron Watry2017-06-141-0/+2
* i965: Use a line end cap width of 0.5 unless smooth lines enabled.Kenneth Graunke2017-06-141-2/+3
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