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* i965: Don't add barrier deps for FB write messages.Kenneth Graunke2016-02-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are never render target reads, so there are no scheduling hazards. Giving the extra flexibility to the scheduler makes it possible to do FB writes as soon as their sources are available, reducing register pressure. It also makes it possible to do the payload setup for more than one FB write message at a time, which could better hide latency. shader-db results on Skylake: total instructions in shared programs: 9110254 -> 9110211 (-0.00%) instructions in affected programs: 2898 -> 2855 (-1.48%) helped: 3 HURT: 0 LOST: 0 GAINED: 1 A reduction in instruction counts is surprising, but legitimate: the three shaders helped were spilling, and reducing register pressure allowed us to issue fewer spills/fills. total cycles in shared programs: 69035108 -> 68928820 (-0.15%) cycles in affected programs: 4412402 -> 4306114 (-2.41%) helped: 4457 HURT: 213 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* st/mesa: enable AoA for gallium drivers reporting GLSL 1.30Dave Airlie2016-02-091-0/+1
| | | | | | Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: add atomic AoA supportDave Airlie2016-02-091-8/+6
| | | | | | | | reuse the sampler deref handling code to do the same thing for atomics. Acked-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: drop unused nonconst sampler functions.Dave Airlie2016-02-092-14/+0
| | | | | | | | Since we fixed the glsl->tgsi conversion we no longer need this function. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: handle indirect samplers in arrays/structs properly (v4.1)Dave Airlie2016-02-091-18/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The state tracker never handled this properly, and it finally annoyed me for the second time so I decided to fix it properly. This is inspired by the NIR sampler lowering code and I only realised NIR seems to do its deref ordering different to GLSL at the last minute, once I got that things got much easier. it fixes a bunch of tests in tests/spec/arb_gpu_shader5/execution/sampler_array_indexing/ v2: fix AoA tests when forced on. I was right I didn't need all that code, fixing the AoA code meant cleaning up a chunk of code I didn't like in the array handling. v3: start generalising the code a bit more for atomics. v3.1: use UniformRemapTable v4: handle uniforms differently using the param_index, and go back to UniformStorage fix issues identified by Timothy with deref handling. v4.1: squash const fix and move handling 1D const out of recursive function. Reviewed-by: Timothy Arceri <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl/ir: add param index to variable.Dave Airlie2016-02-093-4/+11
| | | | | | | | | | | | | We have a requirement to store the index into the mesa parameterlist for uniforms. Up until now we've overwritten var->data.location with this info. However this then stops us accessing UniformStorage, which is needed to do proper dereferencing. Add a new variable to ir_variable to store this value in, and change the two uses to use it correctly. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-085-6/+6
| | | | | | | Its previous name was somewhat misleading, this really behaves like a RW cache flush rather than an invalidation. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Invalidate state cache before L3 partitioning set-up.Francisco Jerez2016-02-081-0/+1
| | | | | | | | | | | The state cache is also L3-backed so it seems sensible to make sure it's clean as we do for other RO caches before repartitioning the L3. This wasn't part of my original L3 partitioning code because I was able to reproduce hangs on Gen7 hardware when the state cache invalidation happened asynchronously with previous 3D rendering, which should no longer be possible after the previous change. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix cache pollution race during L3 partitioning set-up.Francisco Jerez2016-02-081-8/+23
| | | | | | | | | | | | | | | | We need to split the stalling flush from the RO cache invalidation into a different PIPE_CONTROL command to make sure that the top of the pipe invalidation happens after any previous rendering is complete. Otherwise it's possible for previous rendering to pollute the L3 cache in the short window of time between RO invalidation and the completion of the stalling flush. Fixes rendering artifacts on Unigine Heaven, Metro Last Light Redux and Metro 2033 Redux. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93540 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93599 Tested-by: Darius Spitznagel <[email protected]> Tested-by: Martin Peres <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Don't emit unnecessary SEL instruction from emit_image_atomic().Francisco Jerez2016-02-081-1/+1
| | | | | | | | | The SEL instruction with predication mode NONE emitted when the atomic operation doesn't need to be predicated is a no-op and might rely on undocumented hardware behaviour. Noticed by chance while looking at the assembly output. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Update vec4 unit tests for commit 01dacc83ff.Matt Turner2016-02-083-10/+24
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94050
* dri/common: include debug_output.h to silence warningBrian Paul2016-02-081-0/+1
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* tgsi: minor whitespace fixes in tgsi_scan.cBrian Paul2016-02-081-4/+2
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* tgsi: s/true/TRUE/ in tgsi_scan.cBrian Paul2016-02-081-13/+13
| | | | | | | Just to be consistent. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* tgsi: use switches instead of big if/else ifsBrian Paul2016-02-081-24/+36
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* tgsi: break gigantic tgsi_scan_shader() function into piecesBrian Paul2016-02-081-364/+375
| | | | | | | New functions for examining instructions, declarations, etc. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* st/mesa: minor formatting fixes in st_cb_bitmap.cBrian Paul2016-02-081-3/+1
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* mesa: move GL_ARB_debug_output code into new debug_output.c fileBrian Paul2016-02-0812-1318/+1435
| | | | | | | | The errors.c file had grown quite large so split off this extension code into its own file. This involved making a handful of functions non-static. Acked-by: Timothy Arceri <[email protected]>
* gallium/util: whitespace, formatting fixes in u_debug_stack.cBrian Paul2016-02-081-29/+32
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* gallium/util: whitespace, formatting fixes in u_staging.[ch] filesBrian Paul2016-02-082-33/+41
| | | | Still some nonsensical comments.
* gallium/util: switch over to new u_debug_image.[ch] codeBrian Paul2016-02-0810-353/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: put image dumping functions into separate fileBrian Paul2016-02-082-0/+422
| | | | | | To try to reduce the clutter in u_debug.[ch] Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: whitespace, formatting fixes in u_debug.cBrian Paul2016-02-081-95/+106
| | | | Reviewed-by: Marek Olšák <[email protected]>
* trace: add missing pipe_context::clear_texture()Samuel Pitoiset2016-02-081-0/+28
| | | | | | | | This fixes a crash with bin/arb_clear_texture-base-formats and probably some other tests which use clear_texture(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* trace: remove useless MALLOC() in trace_context_draw_vbo()Samuel Pitoiset2016-02-081-11/+6
| | | | | | | There is no need to allocate memory when unwrapping the indirect buf. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa/extensions: Fix NVX_gpu_memory_info lexicographical order.Vinson Lee2016-02-071-1/+2
| | | | | | | | | Fixes MesaExtensionsTest.AlphabeticallySorted. Fixes: 1d79b9958090 ("mesa: implement GL_NVX_gpu_memory_info (v2)") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94016 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: return cloned signature, not the builtin oneIlia Mirkin2016-02-071-1/+2
| | | | | | | | | | | | The builtin data can get released with a glReleaseShaderCompiler call. We're careful everywhere to clone everything that comes out of builtins except here, where we accidentally return the signature belonging to the builtin version, rather than the locally-cloned one. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Rob Herring <[email protected]> Cc: [email protected]
* glsl: make sure builtins are initialized before getting the shaderIlia Mirkin2016-02-071-0/+1
| | | | | | | | | | | | The builtin function shader is part of the builtin state, released when glReleaseShaderCompiler is called. We must ensure that the builtins have been (re)initialized before attempting to link with the builtin shader. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Rob Herring <[email protected]> Cc: [email protected]
* tgsi: use TGSI_WRITEMASK_XYZW instead of hardcoding the maskSamuel Pitoiset2016-02-062-4/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Serge Martin <[email protected]>
* glsl: don't generate transform feedback candidate when not requiredTimothy Arceri2016-02-061-2/+4
| | | | | | | If we are not even looking for one don't bother generating a candidate list. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: replace unreachable code with an assert()Timothy Arceri2016-02-062-65/+38
| | | | | | | | | | | All interface blocks will have been lowered by this point so just use an assert. Returning false would have caused all sorts of problems if they were not lowered yet and there is an assert to catch this later anyway. We also update the tests to reflect this change. Reviewed-by: Kenneth Graunke <[email protected]>
* r600, compute: Do not overwrite pipe_resource.screenJan Vesely2016-02-051-1/+1
| | | | | | | found by inspection. Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: Ignore format for PIPE_BUFFER targetsJan Vesely2016-02-051-1/+1
| | | | | | | | Fixes compute since 7dd31b81fee7fe40bd09cf3fbc324fcc32782479 gallium/radeon: support PIPE_CAP_SURFACE_REINTERPRET_BLOCKS Signed-off-by: Jan Vesely <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* mesa/get: fix a breakage after rebaseMarek Olšák2016-02-051-0/+1
| | | | trivial.
* i965/vec4: don't copy ATTR into 3src instructions with complex swizzlesMatt Turner2016-02-051-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | The vec4 backend, at the end, does this: if (inst->is_3src()) { for (int i = 0; i < 3; i++) { if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0) assert(brw_is_single_value_swizzle(inst->src[i].swizzle)); So make sure that we use the same conditions when trying to copy-propagate. UNIFORMs will be converted to vstride 0 in convert_to_hw_regs, but so will ATTRs when interleaved (as will happen in a GS with multiple attributes). Since the vstride is not set at copy-prop time, infer it by inspecting dispatch_mode and reject ATTRs if they have non-scalar swizzles and are interleaved. Fixes assertion errors in dolphin-generated geometry shaders (or misrendering on opt builds) on Sandybridge or on IVB/HSW with INTEL_DEBUG=nodualobj. Co-authored-by: Ilia Mirkin <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93418 Cc: "11.0 11.1" <[email protected]>
* gallium/radeon: implement query_memory_info (v2)Marek Olšák2016-02-053-2/+39
| | | | | | | v2: don't use DIV_ROUND_UP (no so useful) also return eviction stats Reviewed-by: Alex Deucher <[email protected]>
* st/mesa: implement and enable memory info extensions (v2)Marek Olšák2016-02-052-0/+27
| | | | | | | | v2: assert and return if query_memory_info is not set rebase Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* mesa: implement GL_ATI_meminfo (v2)Marek Olšák2016-02-055-1/+38
| | | | | | | v2: rebase Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* mesa: implement GL_NVX_gpu_memory_info (v2)Marek Olšák2016-02-056-0/+61
| | | | | | | | v2: implement eviction queries properly add gl_memory_info structure Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium: add interface for querying memory usage and sizes (v2)Marek Olšák2016-02-0516-0/+33
| | | | | | | | | | If you're worried about the duplication of some CAPs, we can remove them later. v2: add fields for memory eviction stats Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: remove radeon_info::r600_tiling_configMarek Olšák2016-02-054-24/+9
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsysMarek Olšák2016-02-057-65/+16
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: set num_banks in the winsysMarek Olšák2016-02-057-32/+13
| | | | | | | amdgpu doesn't have to set this, because radeonsi gets it from tile mode arrays by default. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: just get num_tile_pipes from the winsysMarek Olšák2016-02-056-91/+9
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: add an assertion to cik_get_num_tile_pipes (v2)Marek Olšák2016-02-051-1/+4
| | | | | | | v2: print an error to stderr Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: remove an r600-only settingMarek Olšák2016-02-051-1/+0
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: rename & reorder members of radeon_infoMarek Olšák2016-02-0514-95/+103
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* mesa: Fix locking of GLsync objects.Steinar H. Gunderson2016-02-054-49/+66
| | | | | | | | | | | | | | | | | | | | | | | | GLsync objects had a race condition when used from multiple threads (which is the main point of the extension, really); it could be validated as a sync object at the beginning of the function, and then deleted by another thread before use, causing crashes. Fix this by changing all casts from GLsync to struct gl_sync_object to a new function _mesa_get_and_ref_sync() that validates and increases the refcount. In a similar vein, validation itself uses _mesa_set_search(), which requires synchronization -- it was called without a mutex held, causing spurious error returns and other issues. Since _mesa_get_and_ref_sync() now takes the shared context mutex, this problem is also resolved. Fixes bug #92757, found while developing Nageru, my live video mixer (due for release at FOSDEM 2016). v2: Marek: silence warnings, fix declaration after code Signed-off-by: Steinar H. Gunderson <[email protected]> Cc: "11.0 11.1" <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: add placeholder MC and SRBM performance counter groupsNicolai Hähnle2016-02-051-16/+54
| | | | | | | | | | Yet another change motivated by AMD GPUPerfStudio compatibility. These groups are not directly accessible from userspace, and AMD GPUPerfStudio does not actually query them - it just requires them to be there. Hence, adding a placeholder for now. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Marek Olšák <[email protected]>
* radeonsi: re-order the SQ_xx performance counter blocksNicolai Hähnle2016-02-053-39/+42
| | | | | | | | This is yet another change motivated by appeasing AMD GPUPerfStudio's hardcoding of performance counter group numbers. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Marek Olšák <[email protected]>
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