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* st/va: add MJPEG for configLeo Liu2017-08-212-1/+5
| | | | | | | To enable MJPEG HW decode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: reallocate surface with YUYV streamLeo Liu2017-08-211-0/+17
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: detect MJPEG format from bitstreamLeo Liu2017-08-213-0/+10
| | | | | | | | | To find if the format is supported YUYV by sampling factor which is embedded from bitstream. So we could use this info for buffer reallocation on the correct format. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add YUYV format support for target bufferLeo Liu2017-08-212-3/+5
| | | | | | | Make chroma plane optional for YUYV support Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: reallocate surface when interlacedLeo Liu2017-08-211-0/+22
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/video: MJPEG not support stacked video buffersLeo Liu2017-08-211-1/+5
| | | | | | | So we have to detect it for reallocation of de-interlaced buffers Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: make surface allocate functions more usefullyLeo Liu2017-08-212-4/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: reconstruct MJPEG bitstreamLeo Liu2017-08-211-0/+136
| | | | | | | | | The current tier 1 mjpeg firmware only supports at the bitstream level, the later tier 2 support will be at the buffers level with newer hardware. Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add slice parameter handling for MJPEGLeo Liu2017-08-211-1/+23
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add huffman table handling for MJPEGLeo Liu2017-08-211-1/+18
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add iq matrix handling for MJPEGLeo Liu2017-08-211-1/+6
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add picture parameter handling for MJPEGLeo Liu2017-08-211-1/+20
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add handles for MJPEG BuffersLeo Liu2017-08-214-0/+72
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: create decoder for MJPEG formatLeo Liu2017-08-211-3/+6
| | | | | | | Mjpeg doesn't need reference Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add MJPEG picture to contextLeo Liu2017-08-211-0/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/video: add MJPEG supportLeo Liu2017-08-211-0/+8
| | | | | | | v2: add ASIC and Kernel version check Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add MJPEG supportLeo Liu2017-08-211-9/+22
| | | | | | | | | There is no need of dpb buffer for mjpeg codec v2: check dpb_size instead of format Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add MJPEG stream typeLeo Liu2017-08-211-0/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: add MJPEG picture descriptionLeo Liu2017-08-211-0/+59
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: add MJPEG profile and formatLeo Liu2017-08-212-2/+7
| | | | | | | v2: move util video change to here Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: get the target buffer pitch correct for different formatLeo Liu2017-08-211-2/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: update non-resident bindless descriptors if neededSamuel Pitoiset2017-08-211-30/+55
| | | | | | | | | | Only resident bindless descriptors are currently updated and re-uploaded, this makes sure that the non-resident ones are also updated. Signed-off-by: Samuel Pitoiset <[email protected]> Cc: "17.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* dri3: Move up fourcc utility functionLouis-Francis Ratté-Boulianne2017-08-211-21/+21
| | | | | | | It will be needed in next patches. Signed-off-by: Louis-Francis Ratté-Boulianne <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* egl: Add dma_buf_import_modifiers for glvndDaniel Stone2017-08-211-0/+4
| | | | | | | | | | Make sure we advertise the new entrypoints to libglvnd's EGL dispatch. Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reported-by: Emmanuel Gil Peyrot <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101982 Fixes: 4c412293d0e ("egl: advertise EGL_EXT_image_dma_buf_import_modifiers")
* intel/blorp: Adjust intra-tile x when faking rgb with red-onlyTopi Pohjolainen2017-08-211-0/+1
| | | | | | | | | | v2 (Jason): Adjust directly in surf_fake_rgb_with_red() Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910 CC: [email protected] Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* ac/nir: fixup layer/viewport export for GFX9.Dave Airlie2017-08-211-7/+25
| | | | | | | | GFX9 moved where the viewport index export goes. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/bufmgr: s/BO_ALLOC_FOR_RENDER/BO_ALLOC_BUSY/Jason Ekstrand2017-08-204-19/+18
| | | | | | | | | | "Alloc for render" is a terrible name for a flag because it means basically nothing. What the flag really does is allocate a busy BO which someone theorized at one point in time would be more efficient if you're planning to immediately render to it. If the flag really means "alloc a busy BO" we should just call it that. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/tex: Change the flags type on create_for_teximageJason Ekstrand2017-08-201-1/+1
| | | | | | This matches the actual function declaration. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: only copy requested compressed teximage cubemap facesChristoph Haag2017-08-201-2/+2
| | | | | | | | | This is analogous to commit 2259b11 which only fixed the regular case Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102308 Signed-off-by: Christoph Haag <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* i965/tex: Don't pass samples to miptree_create_for_teximageJason Ekstrand2017-08-191-1/+1
| | | | | | | | | | | | | | | | | In 76e2f390f9863a35, when Topi switched num_samples from 0 to 1 for single-sampled, he accidentally switched the last parameter in the call to miptree_create_for_teximage from 0 to 1 thinking it was num_samples when it was actually layout_flags. Switching from 0 to 1 added the MIPTREE_LAYOUT_ACCELERATED_UPLOAD flag which causes us to allocate a busy BO instead of an idle one. This caused the subsequent CPU upload to consistently stall. The end result was a 15% performance drop in the SynMark v7 DrvRes microbenchmark. This restores the old behavior and fixes the performance regression. Reviewed-by: Topi Pohjolainen <[email protected]> Fixes: 76e2f390f9863a356d1419982dec705260d67eff Bugzilla: https://bugs.freedesktop.org/102260 Cc: [email protected]
* anv: Use ISL for emitting null surface states.Kenneth Graunke2017-08-191-16/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use ISL for emitting null surface states.Kenneth Graunke2017-08-197-351/+49
| | | | | | | We handle the Sandybridge multisampled 2D surface hack here, rather than in ISL, because it requires allocating a BO, and is kind of messy. Reviewed-by: Jason Ekstrand <[email protected]>
* isl: Add a null surface fill function.Kenneth Graunke2017-08-194-0/+40
| | | | | | | | | | ISL already offers functions to fill out most kinds of SURFACE_STATE, so why not handle null surfaces too? Null surfaces are simple, so we can just take the dimensions, rather than an entirte fill structure. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Remove tabs in intel_batchbuffer.c.Kenneth Graunke2017-08-181-7/+7
| | | | | | | Our coding style is to use spaces. Some of this was also messed up during my bufmgr import series. (Trivial, just whitespace changes.)
* i965/miptree: Return NONE from texture_aux_usage when fully resolvedJason Ekstrand2017-08-181-1/+14
| | | | | | | | | | | This little optimization improves the performance of SynMark v7 TexFilterTri by almost 10% on Sky Lake GT4 among other improvements. We've been doing it for some time but somehow it got dropped during the miptree refactoring. Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/102258 Cc: "17.2" <[email protected]>
* i965: Stop looking at NewDriverState when emitting 3DSTATE_URBJason Ekstrand2017-08-183-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Looking at NewDriverState is not safe in general. The state atom system is set up to ensure that new bits that get added to NewDriverState get accumulated into the set of bits used when emitting atoms but it doesn't go the other way. If we read NewDriverState, we may not get the full picture because the per-pipeline state (3D or compute) does not get added to NewDriverState before state emit is done. It's especially dangerous to do this from BLORP (either explicitly or implicitly when BLORP calls gen7_upload_urb) because that does not happen during one of the normal state upload paths. This commit solves the problem by whacking all of the per-shader-stage URB sizes to zero whenever we change the total URB size. We still have to flag BRW_NEW_URB_SIZE to ensure that the gen7_urb atom triggers but the actual decision in gen7_upload_urb can now be based entirely on URB sizes rather than on state atoms. This also makes BLORP correct because it just asks for a new URB config whenever the vsize is too small and so any change to the total URB size will trigger blorp to re-emit as well because 0 < vs_entry_size. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Bugzilla: https://bugs.freedesktop.org/102289 Cc: [email protected]
* i965: Mark all EGLimages as non-coherent.Kenneth Graunke2017-08-181-5/+3
| | | | | | | | | | | | | | | | EGLimages are shared with external users, and we don't know what they're going to do with them. They might scan them out. They might access them in a way that doesn't work with our explicit clflushing. It's safest to simply mark them non-coherent. Chris Wilson caught this problem and wrote a similar (though less aggressive) patch to solve it; the miptree code has since undergone a lot of refactoring so I had to rewrite it. Cc: "17.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* broadcom/genxml: Add V3D 3.3 packet definitions.Eric Anholt2017-08-183-0/+802
| | | | | This will be used by the new vc5 gallium driver, and a future Vulkan driver.
* broadcom/genxml: Check the sub-id field when decoding instructions.Eric Anholt2017-08-181-5/+26
| | | | | | VC5 introduces packet variants where the same opcode has behavior that is decided by a sub-id field in the early bits of the packet. Keep iterating over packets until we find the one with the matching sub-id.
* broadcom/genxml: Emit code for default headers for structs as well.Eric Anholt2017-08-181-14/+13
| | | | | | In the vc5 NIR backend, I want to use the XML code-generation to set up pack/unpack of structs for the texture uniforms, and setting up the unpacked copy needs a default header.
* anv: Move a comment that got left behind in the u_vector refactor.Eric Anholt2017-08-182-8/+9
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* gallium/radeon: remove old_fence parameter from r600_gfx_write_event_eopMarek Olšák2017-08-185-12/+17
| | | | | | just use the new scratch buffer. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: prevent a GPU hang after a timestamp eventMarek Olšák2017-08-185-8/+44
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use CLEAR_STATE on SIMarek Olšák2017-08-184-10/+63
| | | | | | | | | This fixes random hangs with Unigine Valley. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102201 Fixes: 064550238ef0 ("radeonsi: use CLEAR_STATE to initialize some registers") Reviewed-by: Nicolai Hähnle <[email protected]>
* Fix build when HAVE_LIBDRM isn't definedJon Turney2017-08-181-0/+4
| | | | | | | | | | | | | | | | make[4]: Entering directory '/wip/mesa/build/src/gallium/targets/dri' CXXLD gallium_dri.la ../../../../src/gallium/auxiliary/pipe-loader/.libs/libpipe_loader_static.a(libpipe_loader_static_la-pipe_loader.o): In function `pipe_loader_get_driinfo_xml': /mesa/build/src/gallium/auxiliary/pipe-loader/../../../../../src/gallium/auxiliary/pipe-loader/pipe_loader.c:117: undefined reference to `pipe_loader_drm_get_driinfo_xml' b4ff5e90 uses pipe_loader_get_driinfo_xml() unconditionally in pipe_loader.c, but it's definition in pipe_loader_get_driinfo_xml() is only built if HAVE_LIBDRM. Arrange to always use the default XML if HAVE_LIBDRM isn't defined. Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Fix missing newlines in perf_debug messages.Kenneth Graunke2017-08-172-3/+3
| | | | perf_debug() doesn't append a newline for you.
* glsl: add a few missing int64 constant propagation casesIlia Mirkin2017-08-182-0/+8
| | | | | | | | | | Fixes KHR-GL45.shader_ballot_tests.ShaderBallotAvailability, which causes some silly swizzles to appear, triggering this optimization to get hit. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Cc: [email protected]
* glsl: set old ldexp operand to NULL when loweringTimothy Arceri2017-08-181-0/+1
| | | | | | | | | This fixes an assert during IR validation in LLVMpipe. Fixes: e2e2c5abd279 (glsl: calculate number of operands in an expression once) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102274 Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* intel/isl: Replace switch statements of doom with a macroJason Ekstrand2017-08-171-96/+39
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Reduce header file duplicationJason Ekstrand2017-08-174-101/+78
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
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