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* svga: Add function svga_resource_type()Neha Bhende2016-09-172-19/+21
| | | | | | | This function returns svga texture type for corresponding pipe texture. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0/ir: fix subops for IMADSamuel Pitoiset2016-09-171-4/+6
| | | | | | | | | Offset was wrong, it's at bit 8, not 4. Also, uses subr instead of sub when src2 has neg. Similar to GK110 now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0/ir: fix comments about instructions infoSamuel Pitoiset2016-09-171-2/+3
| | | | | | | | | The comment for the commutative flags was wrong because OP_MUL is before OP_MAD. While we are at it add missing opcodes, and fix the comment about the short forms. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* mesa: Move buffers-unmapped earlier in check_valid_to_render().Kenneth Graunke2016-09-161-6/+6
| | | | | | | | | | | This needs to be above the switch on API, as that can return true (valid to render) before this error check even had a chance to run. Fixes ESEXT-CTS.draw_elements_base_vertex_tests.invalid_mapped_bos, which worked before commit 72f1566f90c434c7752d8405193eec68d6743246. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]>
* mesa: Expose GL_CONTEXT_FLAGS in ES 3.2.Kenneth Graunke2016-09-161-3/+5
| | | | | | | Fixes four ES32-CTS.context_flags.* tests. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi/compute: Use the HSA abi for non-TGSI compute shaders v3Tom Stellard2016-09-163-18/+761
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches non-TGSI compute shaders over to using the HSA ABI described here: https://github.com/RadeonOpenCompute/ROCm-Docs/blob/master/AMDGPU-ABI.md The HSA ABI provides a much cleaner interface for compute shaders and allows us to share more code in the compiler with the HSA stack. The main changes in this patch are: - We now pass the scratch buffer resource into the shader via user sgprs rather than using relocations. - Grid/Block sizes are now passed to the shader via the dispatch packet rather than at the beginning of the kernel arguments. Typically for HSA, the CP firmware will create the dispatch packet and set up the user sgprs automatically. However, in Mesa we let the driver do this work. The main reason for this is that I haven't researched how to get the CP to do all these things, and I'm not sure if it is supported for all GPUs. v2: - Add comments explaining why we are setting certain bits of the scratch resource descriptor. v3: - Use amdgcn-mesa-mesa3d triple instead of amdgcn--mesa3d. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/compute: Add some more debug printfsTom Stellard2016-09-161-0/+3
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* glsl: remove interpolateAt* instructions for demoted inputsMarek Olšák2016-09-162-0/+15
| | | | | | | This fixes 8 fs-interpolateat* piglit crashes on radeonsi, because it can't handle non-input operands in interpolateAt*. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: fix glGetFramebufferAttachmentParameteriv w/ on-demand FRONT_BACK allocMarek Olšák2016-09-161-2/+14
| | | | | | | This fixes 66 CTS tests on st/mesa. Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* clover: fix getting scalar args api sizeSerge Martin2016-09-161-4/+3
| | | | | | | | This fix getting the size of a struct arg. vec3 types still work ok. Only buit-in args need to have power of two alignment, getTypeAllocSize reports the correct size in all cases. Acked-by: Francisco Jerez <[email protected]>
* ttn: fix warning after 7bf76563eRob Clark2016-09-161-0/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium/docs: document alpha_to_coverage and alpha_to_one blend stateBrian Paul2016-09-161-0/+12
| | | | | | | | The gallium interface defines these like DX10. Note that OpenGL ignores these options if MSAA is disabled or the dest buffer doesn't support MSAA. Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: update comment in st_atom_msaa.cBrian Paul2016-09-161-2/+2
| | | | | | The old comment was a copy and paste mistake. Indent another comment. Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: only enable MSAA coverage options when we have a MSAA bufferBrian Paul2016-09-162-4/+7
| | | | | | | | | | | | | | | | | Regardless of whether GL_MULTISAMPLE is enabled (it's enabled by default) we should not set the alpha_to_coverage or alpha_to_one flags if the current drawing buffer does not do MSAA. This fixes the new piglit gl-1.3-alpha_to_coverage_nop test. ETQW is a game that enables GL_SAMPLE_ALPHA_TO_COVERAGE without MSAA. Shrubs along the side of roads were invisible because fragments with alpha < 0.5 were being discarded (zero coverage). v2: remove ctx->DrawBuffer != NULL check. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* spirv: use subpass image type (v1.1)Dave Airlie2016-09-161-1/+2
| | | | | | | | | | This adds support for the input attachments subpass type to the SPIRV->NIR pass. v1.1: drop handling from vtn_handle_texture Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: add subpass image type (v2)Dave Airlie2016-09-165-2/+20
| | | | | | | | | | | | | | | | | | SPIR-V/Vulkan have a special image type for input attachments called the subpass type. It has different characteristics than other images types. The main one being it can only be an input image to fragment shaders and loads from it are relative to the frag coord. This adds support for it to the GLSL types. Unfortunately we've run out of space in the sampler dim in types, so we need to use another bit. v2: Fixup subpass input name (Jason) Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* isl: Finish tiling filtering for Gen6.Kenneth Graunke2016-09-153-5/+15
| | | | | | | | | | | | | Gen6 only has one additional restriction over Gen7+, so we just add it to the existing gen7 function (which actually covers later gens too). This should stop FINISHME spew when running GL on Sandybridge. v2: Fix bytes per block vs. bits per block confusion (Jason) and rename function to gen6_filter_tiling (Jason and Chad). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: enable ARB_ES3_2_compatibility on gen8+Ilia Mirkin2016-09-151-0/+1
| | | | | | | | Note that ASTC support is not actually mandated for this extension to be exposed. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/nir: Roll set_default_interpolation into lower_fs_inputsJason Ekstrand2016-09-153-39/+26
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use NIR for handling forced per-sample interpolationJason Ekstrand2016-09-153-40/+12
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add a flag to lower_io to force "sample" interpolationJason Ekstrand2016-09-157-21/+38
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use sample interpolation for interpolateAtCentroid in persample modeJason Ekstrand2016-09-151-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | From the ARB_gpu_shader5 spec: The built-in functions interpolateAtCentroid() and interpolateAtSample() will sample variables as though they were declared with the "centroid" or "sample" qualifiers, respectively. When running with persample dispatch forced by the API, we interpolate anything that isn't flat as if it's qualified by "sample". In order to keep interpolateAtCentroid() consistent with the "centroid" qualifier, we need to make interpolateAtCentroid() do sample interpolation instead. Nothing in the GLSL spec guarantees that the result of interpolateAtCentroid is uniform across samples in any way, so this is a perfectly fine thing to do. Fixes 8 of the new dEQP-VK.pipeline.multisample_interpolation.* Vulkan CTS tests that specifically validate consistency between the "sample" qualifier and interpolateAtSample() Signed-off-by: Jason Ekstrand <[email protected]> Cc: "12.0" <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: check for no matrix change in _mesa_LoadMatrixf()Brian Paul2016-09-151-3/+5
| | | | | | | | | | | | | Some apps issue redundant glLoadMatrixf() calls with the same matrix. Try to avoid setting dirty state in that situation. This reduces the number of constant buffer updates by about half in ET Quake Wars. Tested with Piglit, ETQW, Sauerbraten, Google Earth, etc. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* direct-to-native-GL for GLX clients on Cygwin ("Windows-DRI")Jon Turney2016-09-1519-3/+2057
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Structurally, this is very similar to the existing Apple-DRI code, except I have chosen to implement this using the __GLXDRIdisplay, etc. vtables (as suggested originally in [1]), rather than a maze of ifdefs. This also means that LIBGL_ALWAYS_SOFTWARE and LIBGL_ALWAYS_INDIRECT work as expected. [1] https://lists.freedesktop.org/archives/mesa-dev/2010-May/000756.html This adds: * the Windows-DRI extension protocol headers and the windowsdriproto.pc file, for use in building the Windows-DRI extension for the X server * a Windows-DRI extension helper client library * a Windows-specific DRI implementation for GLX clients The server is queried for Windows-DRI extension support on the screen before using it (to detect the case where WGL is disabled or can't be activated). The server is queried for fbconfigID to pixelformatindex mapping, which is used to augment glx_config. The server is queried for a native handle for the drawable (which is of a different type for windows, pixmaps and pbuffers), which is used to augment __GLXDRIdrawable. Various GLX extensions are enabled depending on if the equivalent WGL extension is available.
* mesa: Expose RESET_NOTIFICATION_STRATEGY with KHR_robustness.Kenneth Graunke2016-09-152-3/+10
| | | | | | | | | | | | | | | This is supposed to be exposed with the GL_KHR_robustness extension, which we support on ES 2.0 and later. On desktop GL, it's also exposed by GL_ARB_robustness, which is supported by all drivers ("dummy_true"). so we also allow desktop GL. Fixes: - ES32-CTS.robust.robustness.noResetNotification - ES32-CTS.robust.robustness.loseContextOnReset Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSWJason Ekstrand2016-09-142-0/+2
| | | | | | | | | | | Without this bit set, the value in "L3 Atomic Disable" won't get applied by the hardware so we won't properly get L3 atomic caching. Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of the dEQP-VK.image.atomic_operations.* tests on HSW Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* intel/blorp: Stop setting 3DSTATE_DRAWING_RECTANGLEJason Ekstrand2016-09-143-20/+5
| | | | | | | | | | | | The Vulkan driver sets 3DSTATE_DRAWING_RECTANGLE once to MAX_INT x MAX_INT at the GPU initialization time and never sets it again. The GL driver sets it every time the framebuffer changes. Originally, blorp set it to the size of the drawing area but meant we had to set it back in the Vulkan driver. Instead, we can easily just do that in the GL driver's blorp_exec implementation and not set it in blorp core. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/blorp: Emit 3DSTATE_MULTISAMPLE directlyJason Ekstrand2016-09-143-53/+45
| | | | | | | | | Previously, we relied on a driver hook for 3DSTATE_MULTISAMPLE. However, now that Vulkan and GL use the same sample positions, we can set up 3DSTATE_MULTISAMPLE directly in blorp and delete the driver hook. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: Move Vulkan sample positions to common codeJason Ekstrand2016-09-144-21/+21
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* Revert "tgsi/scan: don't set interp flags for inputs only used by INTERP ↵Marek Olšák2016-09-151-57/+48
| | | | | | | | instructions" This reverts commit 524fd55d2d973f50a5d8bc2255684610f5faae32. Reason: https://bugs.freedesktop.org/show_bug.cgi?id=97808
* i965/vec4: Assert that pull constant load offsets are 16B-aligned.Francisco Jerez2016-09-141-0/+1
| | | | | | | | Non-16B-aligned pull constant loads are unlikely to be particularly useful given that you can get roughly the same effect by using swizzles on the result. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Assert that ATTR regions are register-aligned.Francisco Jerez2016-09-141-0/+1
| | | | | | | It might be useful to actually handle this once copy propagation becomes smarter about register-misaligned offsets. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Don't spill non-GRF-aligned register regions.Francisco Jerez2016-09-142-2/+5
| | | | | | | | | | | A better fix would be to do something along the lines of the FS back-end spilling code and emit a scratch read before any instruction that overwrites the register to spill partially due to a non-zero sub-register offset. In the meantime mark registers used with a non-zero sub-register offset as no-spill to prevent the spilling code from miscompiling the program. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Fix copy propagation for non-register-aligned regions.Francisco Jerez2016-09-141-3/+6
| | | | | | | | | | | | | | This prevents it from trying to propagate a copy through a register-misaligned region. MOV instructions with a misaligned destination shouldn't be treated as a direct GRF copy, because they only define the destination GRFs partially. Also fix the interference check implemented with is_channel_updated() to consider overlapping regions with different register offset to interfere, since the writemask check implemented in the function is only valid under the assumption that the source and destination regions are aligned component by component. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Compare full register offsets in cmod propagation.Francisco Jerez2016-09-141-1/+1
| | | | | | | | | Cmod propagation would misoptimize the program if the destination offset of the generating instruction wasn't exactly the same as the source region offset of the copy instruction. In preparation for adding support for sub-GRF offsets to the VEC4 IR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Assign correct destination offset to rewritten instruction in ↵Francisco Jerez2016-09-141-2/+1
| | | | | | | | | | | | register coalesce. Because the pass already checks that the destination offset of each 'scan_inst' that needs to be rewritten matches 'inst->src[0].offset' exactly, the final offset of the rewritten instruction is just the original destination offset of the copy. This is in preparation for adding support for sub-GRF offsets to the VEC4 IR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Don't coalesce registers with overlapping writes not matching the ↵Francisco Jerez2016-09-141-4/+6
| | | | | | | | MOV source. In preparation for adding support for sub-GRF offsets to the VEC4 IR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Compare full register offsets in opt_register_coalesce nop move ↵Francisco Jerez2016-09-141-1/+1
| | | | | | | | check. In preparation for adding support for sub-GRF offsets to the VEC4 IR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Check that the write offsets match when setting dependency controls.Francisco Jerez2016-09-141-0/+2
| | | | | | | | | For simplicity just assume that two writes to the same GRF with different sub-GRF offsets will potentially interfere and break the dependency control chain. This is in preparation for adding sub-GRF offset support to the VEC4 IR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Change opt_vector_float to keep track of the last offset seen in ↵Francisco Jerez2016-09-141-3/+3
| | | | | | | | | bytes. This simplifies things slightly and makes the pass more correct in presence of sub-GRF offsets. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Simplify src/dst_reg to brw_reg conversion by using byte_offset().Francisco Jerez2016-09-141-7/+8
| | | | | | | This should also have the side effect of fixing convert_to_hw_regs() to handle sub-GRF register offsets. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/ir: Update several stale comments.Francisco Jerez2016-09-145-26/+22
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/ir: Don't print ARF subnr values twice.Francisco Jerez2016-09-142-8/+0
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Print src/dst_reg::offset field consistently for all register files.Francisco Jerez2016-09-141-6/+15
| | | | | | | C.f. 'i965/fs: Print fs_reg::offset field consistently for all register files.'. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Print fs_reg::offset field consistently for all register files.Francisco Jerez2016-09-141-16/+22
| | | | | | | | | | | | The offset printing code in fs_visitor::dump_instruction() was doing things differently for sources and destinations and for each register file -- In some cases it would be added to the base register number fs_reg::nr, in other cases it would follow the base register separated with a plus sign, in other cases (uniforms) it would do both (!). The sub-register offset was also being printed or not rather inconsistently. Fix it. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Misc simplification.Francisco Jerez2016-09-144-6/+6
| | | | | | | Get rid of some leftover redundant arithmetic introduced during the conversion to byte offsets and sizes that can be simplified easily. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Get rid of fs_inst::set_smear().Francisco Jerez2016-09-143-32/+15
| | | | | | | | | | | | | | | | | | | component() was generally a better alternative because of several issues set_smear() had: - It wouldn't take the original stride and offset of the register into account, which means that set_smear() on the result of e.g. another set_smear() call or an offset() call would give a bogus region as result. - It was an inherently destructive operation. See the 'nir_intrinsic_shader_clock' hunk below for how this could lead to subtle bugs in cases where set_smear() was called multiple times on the same register like 'r.set_smear(0), r.set_smear(1)' with the expectation that each call would return a separate value instead of a reference to the same subsequently mutated object. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Use region_contained_in() in compute-to-mrf coalescing pass.Francisco Jerez2016-09-141-3/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Move region_contained_in to the IR header and fix for non-VGRF files.Francisco Jerez2016-09-142-14/+13
| | | | | | | Also changed the argument names since 'src' and 'dst' don't make that much sense outside of the context of copy propagation. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Change region_contained_in() to use byte units.Francisco Jerez2016-09-141-15/+10
| | | | | | | | | | | This makes the function less annoying to use and more accurate -- We shouldn't propagate a copy into a register region that wasn't fully contained in the destination of the copy (IOW, a source region that wasn't fully defined by the copy) just because the number of registers written and read by each instruction happened to get rounded up to the same GRF multiple. Reviewed-by: Iago Toral Quiroga <[email protected]>
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