summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
* vc4: Don't forget to validate code that's got PROG_END on it.Eric Anholt2014-10-281-5/+6
* vc4: Add .dir-locals.el for kernel style in the kernel code.Eric Anholt2014-10-281-0/+12
* vc4: Fix a couple missing '\n's in error output.Eric Anholt2014-10-282-2/+2
* st/mesa: use PIPE_BIND_DISPLAY_TARGET when checking for sRGB capabilityBrian Paul2014-10-281-1/+2
* Revert "st/mesa: set MaxUnrollIterations = 255"Marek Olšák2014-10-281-2/+1
* r300g/vdpau: enable againDavid Heidelberger2014-10-281-0/+1
* r300g: only set clip_halfz for chips with HW TCLMarek Olšák2014-10-281-1/+1
* radeonsi: fix incorrect index buffer max size for lowered 8-bit indicesMarek Olšák2014-10-281-1/+1
* radeonsi: fix polygon mode for points and lines and point/line fill modesMarek Olšák2014-10-281-3/+3
* r600g: fix polygon mode for points and lines and point/line fill modesMarek Olšák2014-10-282-6/+6
* r600g: Implement sm5 UBO/sampler indexingGlenn Kennard2014-10-287-19/+164
* r600g: Implement sm5 interpolation functionsGlenn Kennard2014-10-282-3/+237
* mesa: Add support for the GL_KHR_context_flush_control extensionNeil Roberts2014-10-286-2/+27
* i965/fs: Don't set dependency hints on instructions with spilled destinationsJason Ekstrand2014-10-271-0/+8
* i965/fs: Make scratch write instructions use the correct execution sizeJason Ekstrand2014-10-271-1/+1
* i965/fs: Use correct spill offsetsJason Ekstrand2014-10-271-6/+5
* i965: Use the spill destination for the message header on GEN >= 7Jason Ekstrand2014-10-271-6/+13
* i965/fs: Don't [un]spill multiple registers at a time in SIMD8 modeJason Ekstrand2014-10-271-2/+4
* i965/fs: Use instruction execution sizes when generating scratch reads/writesJason Ekstrand2014-10-271-4/+4
* egl/drm: do not crash when swapping buffers without any renderingLionel Landwerlin2014-10-271-0/+8
* nv50: handle inverted render conditionsTobias Klausmann2014-10-264-10/+51
* freedreno/ir3: consider instruction neighbors in cpRob Clark2014-10-252-11/+178
* freedreno/ir3: always mov tex coordsRob Clark2014-10-251-54/+30
* freedreno: rename a couple debug flagsRob Clark2014-10-253-7/+7
* freedreno/ir3: skip virtual outputs in standalone compilerRob Clark2014-10-251-0/+3
* glx: Fix make check.Mathias Fröhlich2014-10-251-1/+1
* mesa: Add ARB_clip_control.xml to automake.Mathias Fröhlich2014-10-251-0/+1
* freedreno/ir3: standalone compiler updates for ir3testRob Clark2014-10-254-18/+51
* ilo: improve blob decodingChia-I Wu2014-10-251-8/+31
* i965: Skip recalculating URB allocations if the entry size didn't change.Eric Anholt2014-10-244-5/+19
* glsl: Standardize names and fix typosAndres Gomez2014-10-242-7/+7
* i965: Silence unused parameter warning in brw_dump_irIan Romanick2014-10-245-7/+5
* i965: Remove brwIsProgramNativeIan Romanick2014-10-241-9/+0
* mesa: Silence unused parameter warning in _mesa_init_shader_programIan Romanick2014-10-243-7/+6
* mesa: Remove context parameter from dd_function_table::NewShaderProgramIan Romanick2014-10-244-5/+4
* mesa: Make _mesa_init_shader_program staticIan Romanick2014-10-242-6/+3
* mesa: Remove context parameter from _mesa_init_shader_programIan Romanick2014-10-242-3/+3
* glsl_to_tgsi: Remove st_new_shaderIan Romanick2014-10-243-19/+0
* glsl_to_tgsi: Remove st_new_shader_programIan Romanick2014-10-243-16/+0
* i965: Remove brw_new_shader_programIan Romanick2014-10-243-13/+0
* mesa: Silence unused parameter warning in _mesa_clear_shader_program_dataIan Romanick2014-10-246-11/+7
* linker: Rely on _mesa_clear_shader_program_data to clear link informationIan Romanick2014-10-244-14/+34
* mesa: Add some missing clean-up to _mesa_clear_shader_program_dataIan Romanick2014-10-241-1/+14
* mesa: Remove prototypes for nonexistent functionsIan Romanick2014-10-241-9/+0
* ff_fragment_shader: Silence unused parameter warning in smearIan Romanick2014-10-241-6/+6
* meta: Only use _mesa_ClipControl if the extension is supportedIan Romanick2014-10-241-4/+7
* i965/fs: Compute q-values for register allocation manuallyJason Ekstrand2014-10-241-2/+56
* i965/fs: Don't interfere with too many base registersJason Ekstrand2014-10-241-2/+2
* i965/fs: Properly precolor payload registers on GEN5 in SIMD16Jason Ekstrand2014-10-241-1/+10
* i965/fs: Add another use of MAX_VGRF_SIZEJason Ekstrand2014-10-241-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 22:03:37 +0000