summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* nvc0: Enable compute support for PascalBoyan Ding2017-04-273-4/+7
| | | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: Add new launch descriptor format for GP100Boyan Ding2017-04-272-34/+197
| | | | | | | | | | v2: Also handle the the new format in indirect dispatch Use compute class check instead of chipset check Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: Fix index of unk fields in nve4_cp_launch_descBoyan Ding2017-04-271-2/+2
| | | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nouveau: Fix indentation of maxwell compute class definitionsBoyan Ding2017-04-271-2/+2
| | | | | | Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: Don't place scratch buffers above the 32-bit boundaryJason Ekstrand2017-04-271-0/+19
| | | | | | | | | | | | This fixes rendering corruptions in DOOM. Hopefully, it will also make Jenkins a bit more stable as we've been seeing some random failures and GPU hangs ever since turning on 48bit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100620 Fixes: 651ec926fc1 "anv: Add support for 48-bit addresses" Tested-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.1" <[email protected]>
* radv/ac: eliminate unused vertex shader outputs. (v2)Dave Airlie2017-04-273-21/+45
| | | | | | | | | | | This is ported from radeonsi, and I can see at least one Talos shader drops an export due to this, and saves some VGPR usage. v2: use shared code. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi/ac: move vertex export remove to common code.Dave Airlie2017-04-278-164/+235
| | | | | | | | | | | This code can be shared by radv, we bump the max to VARYING_SLOT_MAX here, but that shouldn't have too much fallout. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix regression in descriptor set freeing.Dave Airlie2017-04-271-1/+1
| | | | | | | | | | | Since the host pool changes, Fixes: dEQP-VK.api.descriptor_pool.out_of_pool_memory Fixes: 126d5ad "radv: Use host memory pool for non-freeable descriptors." Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: remove duplicate validationTimothy Arceri2017-04-271-15/+0
| | | | | | | | Varying types have already been validated in apply_type_qualifier_to_variable() by this point. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: use without_array() rather than get_scalar_type()Timothy Arceri2017-04-271-1/+1
| | | | | | | | Here get_scalar_type() was just being use to remove the array after that we converted it back to base_type anyway so just use the without_array() helper. Reviewed-by: Alejandro Piñeiro <[email protected]>
* svga: fix vertex buffer binding issueBrian Paul2017-04-261-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we ran Viewperf11's Maya-03 test 3 we saw warnings about flushing the command buffer with mapped buffers. This happened when transitioning from hardware rendering to a 'draw' fallback path. The problem is the util_set_vertex_buffers_count() function doesn't do exactly what we want in svga_hwtnl_vertex_buffers(). In a case such as dst_count=2, dst={bufA, bufB}, count=1 and src={bufC}, when the function returns we'll have dst_count=2 and dst={bufC, bufB}. What we really want is dst_count=1 and dst={bufC, NULL}. As it was, we were telling the svga device that there were two vertex buffers when in fact we really only needed one for the subsequent drawing command. In this particular case, we first did hardware drawing with {bufA, bufB} then we transitioned to the 'draw' module, consuming vertex data from bufA and bufB and writing the new vertex data to bufC. bufA and bufB are mapped for reading when we flush the command buffer but should not be referenced by the command buffer. The above change fixes that. No Piglit regressions. Also tested with Viewperf, Google Earth, Heaven, etc. VMware bug 1842059 Reviewed-by: Charmaine Lee <[email protected]>
* gallium/util: reduce util_snprintf() calls in debug_flush_might_flush_cb()Brian Paul2017-04-261-5/+6
| | | | | | | We only need to construct the debug message if the mapped_sync flag is set. This should make the function faster since the flag is usually false. Reviewed-by: Charmaine Lee <[email protected]>
* gallium/util: add some comments in u_debug_flush.cBrian Paul2017-04-261-0/+15
| | | | | | Trivial. Reviewed-by: Charmaine Lee <[email protected]>
* svga: Removed the unused label 'done' in svga_validate_surface_view()Charmaine Lee2017-04-261-1/+0
| | | | Trivial fix
* svga: use the winsys interface to invalidate surfaceCharmaine Lee2017-04-261-5/+1
| | | | | | | | | | Instead of directly sending the InvalidateGBSurface command, this patch uses the invalidate_surface interface. Fixes Linux VM piglit failures including ext_texture_array-gen-mipmap, fbo-generatemipmap-array S3TC_DXT1 Reviewed-by: Brian Paul <[email protected]>
* svga: fix format for screen targetCharmaine Lee2017-04-261-0/+26
| | | | | | | | | | | | | | | | | | | This patch revises the fix in commit 606f13afa31c9f041a68eb22cc32112ce813f944 to properly translate the surface format for screen target. Instead of changing the svga format for PIPE_FORMAT_B5G6R5_UNORM to SVGA3D_R5G6B5 for all texture surfaces, this patch only restricts SVGA3D_R5G6B5 for screen target surfaces. This avoids rendering failures when specify a non-vgpu10 format in a vgpu10 context with software renderer. Fixes piglit failures spec@!opengl 1.1@draw-pixels, spec@!opengl 1.1@teximage-colors gl_r3_g3_b2 spec@!opengl 1.1@texwrap formats Tested Xorg with 16bits depth. Also tested with MTT piglit, MTT glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: cache the backing surface handle in the texture objectCharmaine Lee2017-04-265-10/+57
| | | | | | | | | | | | | | | | | | CinebenchR15 not only binds the same texture for rendering and sampling, it actually changes the framebuffer buffer attachment very often, causing a lot of backed surface view to be created and a lot of surface copies to be done. This patch caches the backed surface handle in the texture resource and allows the backed surface view to reuse the backed surface handle. With this patch, the number of backed surface view reduces from 1312 to 3. Unfortunately, this does not eliminate all the surface copies. There are still surface copies involved when we switch from original to backed surface handle for rendering. Tested with CinebenchR15, NobelClinicianViewer, Turbine, Lightsmark2008, MTT glretrace, MTT piglit. Reviewed-by: Brian Paul <[email protected]>
* svga: Update the backing resource only if neededCharmaine Lee2017-04-262-3/+14
| | | | | | | | | | | | | | This patch adds a timestamp in svga_surface structure to keep track of when the backing surface is last sync with the original resource. This helps to avoid unnecessary surface copy from the original resource to the backing surface if the original resource has not since been modified. This reduces the amount of surface copy with CinebenchR15. Tested with CinebenchR15, mtt glretrace. Reviewed-by: Brian Paul <[email protected]>
* svga: Set the surface dirty bit for the right surface viewCharmaine Lee2017-04-261-5/+19
| | | | | | | | For VGPU10, we will render to a backed surface view when the same resource is used for rendering and sampling. In this case, we will mark the dirty bit for the backed surface view. Reviewed-by: Brian Paul <[email protected]>
* svga: Move rendertarget view related fields to hw_clear stateCharmaine Lee2017-04-264-17/+18
| | | | | | | | This patch moves the rendertarget view related fields from svga_hw_draw_state to svga_hw_clear_state where all the hw framebuffer related state resides. Reviewed-by: Brian Paul <[email protected]>
* svga: Move setting the rendered_to flags to framebuffer emit timeCharmaine Lee2017-04-262-18/+28
| | | | | | | Instead of setting the rendered_to flags at set time, this patch moves the setting of the flags to framebuffer emit time. Reviewed-by: Brian Paul <[email protected]>
* svga: add const qualifiers on svga_check_sampler_view_resource_collision()Brian Paul2017-04-262-4/+4
| | | | | | We don't change any of the argument objects. Reviewed-by: Charmaine Lee <[email protected]>
* svga: improve surface view debug messagesBrian Paul2017-04-261-4/+5
| | | | | | The old ones were somewhat cryptic. Reviewed-by: Charmaine Lee <[email protected]>
* svga: add DEBUG_SAMPLERSBrian Paul2017-04-263-1/+4
| | | | | | | | The debug output in svga_create_sampler_state() was controlled by DEBUG_VIEWS but that's not consistent with the other debug output for sampler views. Create/use a new debug flag just for this. Reviewed-by: Charmaine Lee <[email protected]>
* svga: fail screen creation if HW version is too oldBrian Paul2017-04-261-0/+7
| | | | | | | | Tested by verifying 3D acceleration works with HWv8 but not earlier. For HWv7 and older we get the GDI Generic renderer. Reviewed-by: Neha Bhende<[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga: fix error path when kernel is not able to create surfaceDeepak Rawat2017-04-261-15/+18
| | | | | | | | | | | If for some reason kernel is not able to create surface, when no buffer was provided the function vmw_svga_winsys_surface_create should return NULL. This patch fixes the issue where the code was not following the clean up path in case of error, which used to cause SIGSEGV. Reviewed-by: Sinclair Yeh <[email protected]>
* draw: whitespace fixes in draw_pipe_vbuf.cBrian Paul2017-04-261-104/+89
| | | | Remove trailing whitespace, fix formatting, etc. Trivial.
* st/mesa: minor clean-ups in st_update_renderbuffer_surface()Brian Paul2017-04-261-9/+8
| | | | | | | | Remove unneeded parens. Add const qualifiers. Move var decls closer to where they're used. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Neha Bhende<[email protected]>
* nv50,nvc0: disable the TGSI merge registers passSamuel Pitoiset2017-04-262-2/+4
| | | | | | | | | | | | | | | | shader-db results on GK106 (Thanks Karol): total instructions in shared programs : 3931608 -> 3929463 (-0.05%) total gprs used in shared programs : 481255 -> 479014 (-0.47%) total local used in shared programs : 27481 -> 27381 (-0.36%) total bytes used in shared programs : 36031256 -> 36011120 (-0.06%) local gpr inst bytes helped 14 1471 1309 1309 hurt 1 88 384 384 Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* radeonsi: disable the TGSI merge registers passSamuel Pitoiset2017-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 47109 shaders in 29632 tests Totals: SGPRS: 1917364 -> 1916620 (-0.04 %) VGPRS: 1165802 -> 1165202 (-0.05 %) Spilled SGPRs: 1880 -> 1843 (-1.97 %) Spilled VGPRs: 70 -> 65 (-7.14 %) Private memory VGPRs: 1184 -> 1184 (0.00 %) Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread Code Size: 60211356 -> 60192268 (-0.03 %) bytes LDS: 1077 -> 1077 (0.00 %) blocks Max Waves: 428597 -> 428674 (0.02 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 238173 -> 237429 (-0.31 %) VGPRS: 149556 -> 148956 (-0.40 %) Spilled SGPRs: 1263 -> 1226 (-2.93 %) Spilled VGPRs: 25 -> 20 (-20.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 20 -> 16 (-20.00 %) dwords per thread Code Size: 10457904 -> 10438816 (-0.18 %) bytes LDS: 50 -> 50 (0.00 %) blocks Max Waves: 41283 -> 41360 (0.19 %) Wait states: 0 -> 0 (0.00 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: disable the merge registers pass conditionallySamuel Pitoiset2017-04-261-1/+6
| | | | | | | | | | | | | | | | | | | | | The main goal of this pass to merge temporary registers in order to reduce the total number of registers and also to produce optimal TGSI code. In fact, compilers seem to be confused when temporary variables are already merged, maybe because it's done too early in the process. Skipping the pass, reduce both the register pressure and the code size, at least for Nouveau and RadeonSI because they have a real backend compiler. Found by luck while fixing an issue in the TGSI dead code elimination pass which affects tex instructions with bindless samplers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset2017-04-2615-0/+21
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use unsynchronized transfers for shader binary uploadsSamuel Pitoiset2017-04-261-1/+2
| | | | | | | | | | | Because the buffer is new, it can't be referenced by any CS. This can save few CPU cycles by skipping the whole PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: turn si_shader_key::mono into a non-unionMarek Olšák2017-04-263-15/+11
| | | | | | | A merged LS-HS shader needs both fix_fetch and inputs_to_copy for compilation. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: adjust ESGS ring buffer size computation on VIMarek Olšák2017-04-261-1/+4
| | | | | Cc: 17.0 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ONMarek Olšák2017-04-261-2/+3
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct registerMarek Olšák2017-04-262-1/+5
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D imageMarek Olšák2017-04-261-8/+22
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix 1D array shader imagesMarek Olšák2017-04-261-0/+1
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix most things wrong with shader imagesMarek Olšák2017-04-262-12/+24
| | | | | | | | | | | | There are 2 major hw changes: - The address must always point to the address of level 0. GFX9 tiling modes don't allow binding to a non-0 level. - 3D must always be bound as 3D, because 2D and 3D use entirely different tiling modes, and the texture target determines which set of modes is used. Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0Marek Olšák2017-04-261-1/+34
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: tidy up left over APPLE_vertex_array_object semanticsTimothy Arceri2017-04-264-43/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: inline bind_vertex_array() helperTimothy Arceri2017-04-261-17/+6
| | | | | | The previous commit removed the only other user of this function. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: drop APPLE_vertex_array_object supportTimothy Arceri2017-04-2611-100/+19
| | | | | | | | | | | | | | | | | | | | | Shared context support for VAOs was dropped in 0b2750620b65. From the ARB_vertex_array_object spec: "This extension differs from GL_APPLE_vertex_array_object in that client memory cannot be accessed through a non-zero vertex array object. It also differs in that vertex array objects are explicitly not sharable between contexts." Nobody should be using this extension over ARB_vertex_array_object anymore so just drop it rather than adding locking back just for VAOs created from these functions. For reference the Nvidia blob doesn't expose this extension. Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Enable userspace fence checking.Bas Nieuwenhuizen2017-04-263-3/+36
| | | | | | | | | | v2: - Added some error handling. - memset the buffer to 0. v3: Added assert for buffer size. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965: Remove unused variable 'options'Matt Turner2017-04-251-2/+0
| | | | Should have been removed in commit ad55b1a7701a
* glsl: Initialize current_varMatt Turner2017-04-251-1/+1
| | | | CID: 1324644 (Uninitialized pointer field)
* radv/ac: setup mrt exports then export them in one go. (v2)Dave Airlie2017-04-251-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Noticed while looking at Sascha Willems deferred shaders. This is a bit of an llvm workaround, llvm was producing this: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 s_waitcnt vmcnt(0) ; BF8C0F70 exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v4, v12, v5 ; D2960004 00020B0C v_cvt_pkrtz_f16_f32_e64 v5, v14, 1.0 ; D2960005 0001E50E exp mrt1 v4, v4, v5, v5 compr ; C400041F 00000504 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 After this change: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 s_waitcnt vmcnt(0) ; BF8C0F70 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 v_cvt_pkrtz_f16_f32_e64 v5, v12, v5 ; D2960005 00020B0C v_cvt_pkrtz_f16_f32_e64 v7, v14, 1.0 ; D2960007 0001E50E exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt1 v5, v5, v7, v7 compr ; C400041F 00000705 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 No waitcnt for exports are emitted. v2: fixup index->mrt mapping (Bas). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: overhaul vs output/ps input routingDave Airlie2017-04-253-37/+55
| | | | | | | | In order to cleanly eliminate exports rewrite the code first to mirror how radeonsi works for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: move point coord after layer/viewport.Dave Airlie2017-04-251-6/+7
| | | | | | | | These need to be ordered as per shader enum ordering, I'll rewrite this soon, but this is a bug fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 03:22:45 +0000