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* nir: Add opcodes for saturated vector math.Eric Anholt2015-10-232-0/+51
* vc4: Add dumping of VC4_PACKET_GL_INDEXED_PRIMITIVE.Eric Anholt2015-10-231-1/+22
* vc4: Add a workaround for HW-2116 (state counter wrap fails).Eric Anholt2015-10-233-6/+40
* vc4: Fix missing \n in a perf_debug().Eric Anholt2015-10-231-1/+1
* i965/fs: Allow copy propagating into new surface access opcodesKristian Høgsberg Kristensen2015-10-231-0/+15
* i965/fs: Optimize ssbo storesKristian Høgsberg Kristensen2015-10-231-30/+25
* i965/fs: Drop offset_reg temporary in ssbo loadKristian Høgsberg Kristensen2015-10-231-5/+3
* i965/fs: Avoid scalar destinations in emit_uniformize()Kristian Høgsberg Kristensen2015-10-231-4/+11
* i965/fs: Don't uniformize surface index twiceKristian Høgsberg Kristensen2015-10-231-2/+0
* i965/fs: Use unsigned immediate 0 when eliminating SHADER_OPCODE_FIND_LIVE_CH...Kristian Høgsberg Kristensen2015-10-231-1/+1
* i965/fs: Read all components of a SSBO field with one sendKristian Høgsberg Kristensen2015-10-231-18/+7
* i965: Don't use message headers for untyped readsKristian Høgsberg Kristensen2015-10-232-3/+2
* i965/vec4: check opcode on vec4_instruction::reads_flag(channel)Alejandro Piñeiro2015-10-231-2/+2
* vc4: Use Rob's NIR-based user clip lowering.Eric Anholt2015-10-234-69/+14
* vc4: Also dump the decimation mode for resolved stores.Eric Anholt2015-10-231-2/+4
* vc4: Use VC4_GET_FIELD and other defines in dumping VC4_RENDER_CONFIG.Eric Anholt2015-10-231-10/+10
* vc4: Add a sentinel after simulator buffers for buffer overflow detection.Eric Anholt2015-10-231-1/+11
* glsl: fix shader storage block member rules when adding program resourcesSamuel Iglesias Gonsalvez2015-10-231-6/+27
* ilo: add support for scratch spacesChia-I Wu2015-10-2310-16/+133
* ilo: fix scratch space setup in coreChia-I Wu2015-10-2311-133/+327
* glsl: remove excess location qualifier validationTimothy Arceri2015-10-231-48/+22
* virgl/vtest: add vtest driverDave Airlie2015-10-2310-2/+1242
* virgl: add driver for virtio-gpu 3D (v2)Dave Airlie2015-10-2328-0/+5918
* tgsi: try and handle overflowing shaders. (v2)Dave Airlie2015-10-232-3/+9
* tgsi: add option to dump floats as hex valuesDave Airlie2015-10-233-2/+30
* svga: Condition preemptive flush on draw emissionSinclair Yeh2015-10-224-5/+25
* svga: try to avoid index generation for some primitive typesBrian Paul2015-10-221-0/+14
* svga: avoid provoking vertex conversion when possibleBrian Paul2015-10-221-1/+14
* svga: detect constant color writes in fragment shadersBrian Paul2015-10-225-2/+77
* mesa: check for unchanged line width before error checkingBrian Paul2015-10-221-3/+4
* st/mesa: use _mesa_RasterPos() when possibleBrian Paul2015-10-221-0/+10
* tnl: remove t_rasterpos.cBrian Paul2015-10-222-479/+0
* drivers/common: use _mesa_RasterPos instead of _tnl_RasterPosBrian Paul2015-10-221-1/+2
* mesa: copy rasterpos evaluation code into core MesaBrian Paul2015-10-222-0/+444
* vbo: optimize vertex copying when 'wrapping'Brian Paul2015-10-222-17/+14
* radeon/uvd: don't expose HEVC on old UVD hw (v3)Alex Deucher2015-10-221-32/+18
* i965/vec4: print predicate control at brw_vec4 dump_instructionAlejandro Piñeiro2015-10-223-3/+5
* i965/vec4: use an envvar to decide to print the assembly on cmod_propagation ...Alejandro Piñeiro2015-10-222-2/+2
* i965/vec4: Add unit tests for cmod propagation passAlejandro Piñeiro2015-10-222-0/+829
* i965/vec4: adding vec4_cmod_propagation optimizationAlejandro Piñeiro2015-10-224-0/+160
* i965/vec4: track and use independently each flag channelAlejandro Piñeiro2015-10-223-14/+52
* i965/vec4: nir_emit_if doesn't need to predicate based on all the channelsAlejandro Piñeiro2015-10-221-1/+3
* i965/vec4/gs: Fix signed/unsigned comparison warning.Matt Turner2015-10-221-1/+1
* i965/fs: Emit a single ADD instruction for SET_SAMPLE_ID on Gen8+.Matt Turner2015-10-221-1/+1
* i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID.Matt Turner2015-10-221-5/+5
* i965/fs: Trim unneeded channels in SampleID setup.Matt Turner2015-10-221-6/+6
* i965/fs: Use type-W for immediate in SampleID setup.Matt Turner2015-10-222-3/+3
* i965/vec4: Initialize LOD to 0.0f for textureQueryLevels() and texture().Matt Turner2015-10-221-0/+12
* i965: Note that the UV immediate type is Gen6+.Matt Turner2015-10-221-1/+1
* gallivm: Translate all util_cpu_caps bits to LLVM attributes.Jose Fonseca2015-10-221-2/+34
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