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* ilo: embed ilo_state_vf in ilo_ve_stateChia-I Wu2015-06-1512-330/+146
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* ilo: embed ilo_state_urb in ilo_state_vectorChia-I Wu2015-06-159-350/+185
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* ilo: embed ilo_state_sol in ilo_shaderChia-I Wu2015-06-158-151/+154
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* ilo: embed ilo_state_cc in ilo_blend_stateChia-I Wu2015-06-1513-979/+462
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* ilo: embed ilo_state_raster in ilo_rasterizer_stateChia-I Wu2015-06-1512-1186/+457
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* ilo: embed ilo_state_viewport in ilo_viewport_stateChia-I Wu2015-06-1512-369/+142
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* ilo: replace ilo_sampler_cso with ilo_state_samplerChia-I Wu2015-06-156-590/+258
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* ilo: replace ilo_view_surface with ilo_state_surfaceChia-I Wu2015-06-159-1035/+205
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* ilo: replace ilo_zs_surface with ilo_state_zsChia-I Wu2015-06-158-479/+105
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* ilo: add ilo_state_psChia-I Wu2015-06-153-0/+848
| | | | We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs,ps}.
* ilo: add ilo_state_{vs,hs,ds,gs}Chia-I Wu2015-06-153-0/+919
| | | | | We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs} and ps payload.
* ilo: add ilo_state_sbeChia-I Wu2015-06-153-0/+455
| | | | We want to replace ilo_kernel_routing with ilo_state_sbe.
* ilo: add ilo_state_vfChia-I Wu2015-06-153-0/+637
| | | | We want to replace ilo_ve_state with ilo_state_vf.
* ilo: add ilo_state_urbChia-I Wu2015-06-153-0/+874
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* ilo: add ilo_state_solChia-I Wu2015-06-153-0/+448
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* ilo: add ilo_state_ccChia-I Wu2015-06-153-0/+1091
| | | | We want to replace ilo_dsa_state and ilo_blend_state with ilo_state_cc.
* ilo: add ilo_state_rasterChia-I Wu2015-06-153-0/+1262
| | | | We want to replace ilo_rasterizer_state with ilo_state_raster.
* ilo: add ilo_state_viewportChia-I Wu2015-06-143-0/+512
| | | | | We want to replace ilo_viewport_cso and ilo_scissor_state with ilo_state_viewport.
* ilo: add ilo_state_samplerChia-I Wu2015-06-143-0/+847
| | | | We want to replace ilo_sampler_cso with ilo_state_sampler.
* ilo: add ilo_state_surfaceChia-I Wu2015-06-143-0/+1297
| | | | We want to replace ilo_view_surface with ilo_state_surface.
* ilo: add ilo_state_zsChia-I Wu2015-06-143-0/+822
| | | | | | We want to replace ilo_zs_surface with ilo_state_zs. One noteworthy difference is that ilo_state_zs always aligns level 0 to 8x4 when HiZ is enabled. HiZ will not be enabled for 1D surfaces as a result.
* ilo: update genhw headersChia-I Wu2015-06-1411-282/+298
| | | | | | | | | | | | | | | | | | | Generate these new enums enum gen_reorder_mode; enum gen_clip_mode; enum gen_front_winding; enum gen_fill_mode; enum gen_cull_mode; enum gen_pixel_location; enum gen_sample_count; enum gen_inputattr_select; enum gen_msrast_mode; enum gen_prefilter_op; Correct the type of GEN6_SAMPLER_DW0_BASE_LOD. Rename gen_logicop_function, gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and others.
* ilo: add ilo_image_disable_aux()Chia-I Wu2015-06-143-8/+28
| | | | | When aux bo allocation fails, ilo_image_disable_aux() should be called to disable aux buffer.
* ilo: add array_size and level_count to ilo_imageChia-I Wu2015-06-142-0/+6
| | | | We will use them for bound checking.
* ilo: add pipe_texture_target to ilo_imageChia-I Wu2015-06-146-23/+18
| | | | Save the target in ilo_image instead of passing it around.
* ilo: fix "Render Cache Read Write Mode"Chia-I Wu2015-06-145-28/+12
| | | | | It needs be set to R/W only when using certain messages via DP render cache. Since we only use RT wrties with the render cache, we never need to set it.
* ilo: avoid resource owning in coreChia-I Wu2015-06-147-142/+27
| | | | It is up to the users whether to reference count the BOs or not.
* ilo: assert core objects are zero-initializedChia-I Wu2015-06-146-2/+29
| | | | | Core objects are usually embedded inside calloc()'ed objects and we expect them to be zero-initialized.
* radeon/llvm: Handle LLVM backend rename from R600 to AMDGPUTom Stellard2015-06-121-0/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallivm: Only build lp_profile() body when PROFILE is definedTom Stellard2015-06-121-1/+1
| | | | | | | The only use of lp_profile() is wrapped in #if defined(PROFILE), so there is no reason to build it unless this macro is defined. Reviewed-by: Jose Fonseca <[email protected]>
* glsl: fix compile error messageTimothy Arceri2015-06-131-1/+1
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* i965/gen8+: Add aux buffer alignment assertionsBen Widawsky2015-06-121-0/+22
| | | | | | | | | | | | | | This helped find the incorrect HALIGN values from the previous patches. v2: Add PRM references for assertions (Chad) v3: Remove duplicated part of commit message, assert num_samples > 1, instead of num_samples > 0. (Chad) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen9: Set HALIGN_16 for all aux buffersBen Widawsky2015-06-121-3/+19
| | | | | | | | | | | | | | | | | | | Just like the previous patch, but for the GEN9 constraints. v2: bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address this, move the check to where the gen8 check is, and do the appropriate conditional there. v3: Remove stray whitespace introduced in v2 (Chad) Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part about gen7 (Chad). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (v1) Reviewed-by: Jordan Justen <[email protected]> (v1) Reviewed-by: Chad Versace <[email protected]>
* i965/gen8: Correct HALIGN for AUX surfacesBen Widawsky2015-06-123-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This restriction was attempted in this commit: commit 47053464630888f819ef8cc44278f1a1220159b9 Author: Anuj Phogat <[email protected]> Date: Fri Feb 13 11:21:21 2015 -0800 i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT However, the commit itself doesn't achieve the desired goal as determined by the asserts which the next patch adds. mcs_mt is NULL (never set) we're in the process of allocating the mcs_mt miptree when we get to this function. I didn't check, but perhaps this would work with blorp, however, meta clears allocate the miptree structure (which AFAICT needs the alignment also) way before it allocates using meta clears where the renderbuffer is allocated way before the aux buffer. The restriction is referenced in a few places, but the most concise one [IMO] from the spec is for Gen9. Gen8 loosens the restriction in that it only requires this for non-msrt surface. When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must be used. With the code before the miptree layout flag rework (patches preceding this), accomplishing this workaround is very difficult. v2: bugfix: Don't set HALIGN16 for gens before 8 (Chad) v3: non-trivial rebase Signed-off-by: Ben Widawsky <[email protected]> Cc: Neil Roberts <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Extract tiling from fast clear decisionBen Widawsky2015-06-122-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several constraints when determining if one can fast clear a surface. Some of these are alignment, pixel density, tiling formats, and others that vary by generation. The helper function which exists today does a suitable job, however it conflates "BO properties" with "Miptree properties" when using tiling. I consider the former to be attributes of the physical surface, things which are determined through BO allocation, and the latter being attributes which are derived from the API, and having nothing to do with the underlying surface. Determining tiling properties and creating miptrees are related operations (when we allocate a BO for a miptree) with some disjoint constraints. By extracting the decisions into two distinct choices (tiling vs. miptree properties), we gain flexibility throughout the code to make determinations about when we can or cannot fast clear strictly on the miptree. To signify this change, I've also renamed the function to indicate it is a distinction made on the miptree. I am torn as to whether or not it was a good idea to remove "non_msrt" since it's a really nice thing for grep. v2: Reword some comments (Chad) intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad) Make full if ladder for gens in above function (Chad) Signed-off-by: Ben Widawsky <[email protected]> Cc: Topi Pohjolainen <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen9: Only allow Y-Tiled MCS buffersBen Widawsky2015-06-121-0/+2
| | | | | | | | | | | | | | | | | | | For GEN9, much of the logic to use X-Tiled buffers has been stripped out. It is still supported in some places, but it's never desirable. Unfortunately we don't yet have the ability to have Y-Tiled scanout (see: http://patchwork.freedesktop.org/patch/46984/), NOTE: This patch shouldn't actually do anything since SKL doesn't yet use fast clears (they are disabled because they are causing regressions). THerefore, the only case we can get to this function on SKL is by way of intel_update_winsys_renderbuffer_miptree. v2: Update commit message to be more clear that the NOTE is for SKL only. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-129-75/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I think pretty much everyone agrees that having more than a single bool as a function argument is bordering on a bad idea. What sucks about the current code is in several instances it's necessary to propagate these boolean selections down to lower layers of the code. This requires plumbing (mechanical, but still churn) pretty much all of the miptree functions each time. By introducing the flags paramater, it is possible to add miptree constraints very easily. The use of this, as is already the case, is sometimes we have some information at the time we create the miptree that needs to be known all the way at the lowest levels of the create/allocation, disable_aux_buffers is currently one such example. There will be another example coming up in a few patches. v2: Tab fix. (Ben) Long line fixes (Topi) Use anonymous enum instead of #define for layout flags (Chad) Use 'X != 0' instead of !!X (everyone except Chad) v3: Some non-trivial conflict resolution on top of Anuj's patches. Signed-off-by: Ben Widawsky <[email protected]> Cc: "Pohjolainen, Topi" <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* glsl: enforce restriction on AoA interface blocks in GLSL ES 3.10Timothy Arceri2015-06-131-0/+11
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: enforce fragment shader input restrictions in GLSL ES 3.10Timothy Arceri2015-06-131-0/+45
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: enforce output variable rules for GLSL ES 3.10Timothy Arceri2015-06-131-0/+49
| | | | | | Some rules are already applied this just adds the missing ones. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/nir: Support barrier intrinsic functionJordan Justen2015-06-121-0/+4
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-125-0/+45
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add brw_barrier to emit a Gateway Barrier SENDJordan Justen2015-06-122-0/+32
| | | | | | | | | | | | This will be used to implement the Gateway Barrier SEND needed to implement the barrier function. v2: * notify => gateway_notify (Ken) * combine short lines of brw_barrier proto/decl (mattst88) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add brw_WAIT to emit wait instructionJordan Justen2015-06-122-0/+23
| | | | | | | | | | | This will be used to implement the barrier function. v2: * Rename to brw_WAIT (mattst88) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add notification registerJordan Justen2015-06-121-0/+16
| | | | | | | | | | | | This will be used by the wait instruction when implementing the barrier() function. v2: * Changes suggested by mattst88 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Disassemble Gateway SEND messagesJordan Justen2015-06-121-0/+16
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/inst: Add gateway_notify and gateway_subfuncid fieldsJordan Justen2015-06-121-3/+11
| | | | | | | | | | | | | | | These fields will be used when emitting a send for the barrier function. Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor v2: * notify => gateway_notify (Ken) * define bits for gen4-gen6 (bwidawsk, Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* nir: Add barrier intrinsic functionJordan Justen2015-06-122-1/+4
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* glsl: Add builtin barrier() functionChris Forbes2015-06-121-0/+18
| | | | | | | [[email protected]: Add CS support] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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