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* gallium/u_threaded: align batches and call slots to 16 bytesMarek Olšák2017-06-052-3/+17
* st/mesa: don't load cached TGSI shaders on demandMarek Olšák2017-06-051-1/+6
* Android: use bionic pthread_barrier_* if possibleChih-Wei Huang2017-06-051-1/+1
* r600: fix incorrect and missing bit field in register headers.Dave Airlie2017-06-051-3/+4
* radv: use ac_compute_surfaceNicolai Hähnle2017-06-051-386/+6
* radv: prepare fmask surface creationDave Airlie2017-06-052-7/+7
* radv: use amdgpu_addr_createNicolai Hähnle2017-06-054-158/+5
* radv: stop using radv_amdgpu_winsys::familyNicolai Hähnle2017-06-052-2/+2
* radv: use ac_gpu_infoNicolai Hähnle2017-06-055-229/+13
* radv: remove radeon_info::nameNicolai Hähnle2017-06-053-30/+27
* radv: use ac_surface data structuresNicolai Hähnle2017-06-058-153/+81
* radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}Nicolai Hähnle2017-06-053-12/+13
* radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREENicolai Hähnle2017-06-052-3/+1
* radv: remove radeon_surf_level::nblk_zNicolai Hähnle2017-06-053-6/+1
* radv: remove radeon_surf_level::dcc_enabledNicolai Hähnle2017-06-055-6/+7
* radv: remove radeon_surf_level::pitch_bytesNicolai Hähnle2017-06-055-13/+3
* radv: add surface helper variable in radv_GetImageSubresourceLayoutNicolai Hähnle2017-06-051-6/+7
* radv: fewer than 8 RBs are possibleNicolai Hähnle2017-06-051-2/+0
* ac/surface/gfx6: explicitly support S8 surfacesNicolai Hähnle2017-06-051-25/+50
* ac/nir: set workgroup size attribute to correct value.Dave Airlie2017-06-051-3/+32
* ac: add new helper function to add a integer target dependent function attr.Dave Airlie2017-06-052-0/+15
* radv: add external memory support.Dave Airlie2017-06-053-14/+183
* radv: Add VkPhysicalDeviceIDProperties support.Bas Nieuwenhuizen2017-06-052-2/+23
* radv: Add support for external queue family.Bas Nieuwenhuizen2017-06-051-1/+6
* radv/formats: reverse how the image format properties KHR2 is handledDave Airlie2017-06-051-30/+46
* radv: Dirty all descriptors sets when changing the pipeline.Bas Nieuwenhuizen2017-06-032-8/+14
* radv: Set both compute and graphics SGPRS on descriptor set flush.Bas Nieuwenhuizen2017-06-031-50/+50
* i965: Order write of query availablity with earlier writesChris Wilson2017-06-031-2/+11
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-028-1/+15
* st/mesa: Add support for ARB_post_depth_coverageLyude2017-06-022-1/+7
* gallium: Add a cap to check if the driver supports ARB_post_depth_coverageLyude2017-06-0217-0/+18
* gallium: Add TGSI shader token for ARB_post_depth_coverageLyude2017-06-023-0/+9
* nvc0: disable BGRA8 images on FermiLyude2017-06-021-5/+14
* i965: Simplify l3 way size computationsAnuj Phogat2017-06-021-10/+2
* i965: Add and initialize l3_banks field for gen7+Anuj Phogat2017-06-022-3/+27
* i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table (v2)Chad Versace2017-06-022-92/+6
* st/dri: Use fence extension in drisw.cGurchetan Singh2017-06-021-0/+2
* st/dri: move fence implemention into separate fileGurchetan Singh2017-06-024-203/+263
* mesa: document range of SampleCoverageValue, MinSampleShadingValueBrian Paul2017-06-021-2/+2
* xlib: fix glXGetCurrentDisplay() failureBrian Paul2017-06-024-5/+18
* radv: realign cp dma code with radeonsiDave Airlie2017-06-021-86/+70
* radv: bump some base addresses to 64-bits.Dave Airlie2017-06-021-9/+9
* radv: factor out eop event writing code. (v2)Dave Airlie2017-06-024-65/+82
* radv: factor out si_emit_wait_fence code.Dave Airlie2017-06-024-22/+20
* intel/blorp: Handle gen6 stencil/HiZ offsets in the back-endJason Ekstrand2017-06-015-74/+41
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-013-9/+64
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-013-9/+6
* intel/isl: Add a new layout for HiZ and stencil on Sandy BridgeJason Ekstrand2017-06-012-5/+197
* intel/isl: Generate phys_total_el from isl_calc_phys_extentJason Ekstrand2017-06-011-68/+97
* intel/isl: Don't check array pitch for gen4 3D texturesJason Ekstrand2017-06-011-1/+0
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