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* radv: fewer than 8 RBs are possibleNicolai Hähnle2017-06-051-2/+0
| | | | | | This fixes the subsequent assertion on Bonaire. Reviewed-by: Dave Airlie <[email protected]>
* ac/surface/gfx6: explicitly support S8 surfacesNicolai Hähnle2017-06-051-25/+50
| | | | | | This is needed by radv for dEQP-VK.renderpass.simple.stencil Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: set workgroup size attribute to correct value.Dave Airlie2017-06-051-3/+32
| | | | | | | | | | | | This ports: 55445ff1891724c78e6573d2f8c721e14c0449fc from radeonsi radeonsi: tell LLVM not to remove s_barrier instructions LLVM 5.0 removes s_barrier instructions if the max-work-group-size attribute is not set. What a surprise. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: add new helper function to add a integer target dependent function attr.Dave Airlie2017-06-052-0/+15
| | | | | | | This is needed to add the max workgroup size attribute. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add external memory support.Dave Airlie2017-06-053-14/+183
| | | | | | | | | | | | | | | | | | | | | | | This adds support for exporting 2D images, to an opaque fd. This implements the: VK_KHX_external_memory_capabilities VK_KHX_external_memory VK_KHX_external_memory_fd extensions. These are used by SteamVR, we should work with anv to decide if we should ship these under an env var or something. v2 (Bas): - Don't expose the semaphore ext without implementing it. - Only export the capabilities ext as instance ext. - Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX. Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Bas Nieuwenhuizen <[email protected]>
* radv: Add VkPhysicalDeviceIDProperties support.Bas Nieuwenhuizen2017-06-052-2/+23
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add support for external queue family.Bas Nieuwenhuizen2017-06-051-1/+6
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/formats: reverse how the image format properties KHR2 is handledDave Airlie2017-06-051-30/+46
| | | | | | | This just aligns with how anv does it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Dirty all descriptors sets when changing the pipeline.Bas Nieuwenhuizen2017-06-032-8/+14
| | | | | | | | | Sets could have been ignored during previous descriptor set flush due to the shader not using them and therefore no SGPR being assigned. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
* radv: Set both compute and graphics SGPRS on descriptor set flush.Bas Nieuwenhuizen2017-06-031-50/+50
| | | | | | | | | | We clear the descriptors_dirty array afterwards, so the SGPRs for the other pipeline don't get updated on the flush for that other draw/dispatch, so we have to make sure we do it immediately. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
* i965: Order write of query availablity with earlier writesChris Wilson2017-06-031-2/+11
| | | | | | | | | | | | Currently we signal the availabilty of the query result using an unordered pipe-control write. As it is unordered, it may be executed before the write of the query result itself - and so an observer may read the query result too early. Fix this by requesting that the write of the availablity flag is ordered after earlier pipe control writes. Testcase: piglit/arb_query_buffer_object-qbo/*async* Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* nvc0: Add support for ARB_post_depth_coverageLyude2017-06-028-1/+15
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: Add support for ARB_post_depth_coverageLyude2017-06-022-1/+7
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add a cap to check if the driver supports ARB_post_depth_coverageLyude2017-06-0217-0/+18
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add TGSI shader token for ARB_post_depth_coverageLyude2017-06-023-0/+9
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: disable BGRA8 images on FermiLyude2017-06-021-5/+14
| | | | | | | | | | | | BGRA8 image stores on Fermi don't work, which results in breaking PBO downloads, such that they always return 0x0. Discovered this through a glamor bug, and confirmed it does indeed break a good number of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888 Fixes: 8e7893eb53213 ("nvc0: add support for BGRA8 images") Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* i965: Simplify l3 way size computationsAnuj Phogat2017-06-021-10/+2
| | | | | | | | | | | By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. V2: Keep the get_l3_way_size() function. Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Add and initialize l3_banks field for gen7+Anuj Phogat2017-06-022-3/+27
| | | | | | | | | | | This new field helps simplify l3 way size computations in next patch. V2: Initialize the l3_banks to 0 in macros. Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table (v2)Chad Versace2017-06-022-92/+6
| | | | | | | | | | | | | | | | | When given an *unsupported* mesa_format, brw_isl_format_for_mesa_format() returned 0, a *valid* isl_format, ISL_FORMAT_R32G32B32A32_FLOAT. The problem is that brw_isl_format_for_mesa_format's inner table used 0 instead of ISL_FORMAT_UNSUPPORTED to indicate unsupported mesa formats. Some callers of brw_isl_format_for_mesa_format() were aware of this weirdness, and worked around it. This patch removes those workarounds. v2: Ensure that all array elements are initialized to ISL_FORMAT_UNSUPPORTED, even when new formats are added to enum mesa_format, by using an designated range initializer. Reviewed-by: Matt Turner <[email protected]>
* st/dri: Use fence extension in drisw.cGurchetan Singh2017-06-021-0/+2
| | | | | | This is desirable for synchronization in virtual machines. Reviewed-by: Marek Olšák <[email protected]>
* st/dri: move fence implemention into separate fileGurchetan Singh2017-06-024-203/+263
| | | | | | | | | | | Since the fence implementation is not dri2.c specific, put it in a separate file. This way SW implementations can use this extension too. v2: Don't depend on dri2.c for extensions (Emil) v3: Make this patch only move extension into a separate file (Chad). Reviewed-by: Marek Olšák <[email protected]>
* mesa: document range of SampleCoverageValue, MinSampleShadingValueBrian Paul2017-06-021-2/+2
| | | | Trivial.
* xlib: fix glXGetCurrentDisplay() failureBrian Paul2017-06-024-5/+18
| | | | | | | | | | | | | | | | | glXGetCurrentDisplay() has been broken for years and nobody noticed until recently. This change adds a new XMesaGetCurrentDisplay() that the GLX emulation API can call, just as we did for glXGetCurrentContext(). Tested by hacking glxgears to call glXGetCurrentContext() before and after glXMakeCurrent() to verify the return value is NULL beforehand and the same as the opened display afterward. Also tested by Tom Hudson with his tests programs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100988 Cc: [email protected] Tested-by: Tom Hudson <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* radv: realign cp dma code with radeonsiDave Airlie2017-06-021-86/+70
| | | | | | | | This reworks this code to be like radeonsi, which will make it easier to add GFX9 support to it in the future. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump some base addresses to 64-bits.Dave Airlie2017-06-021-9/+9
| | | | | | | | For GFX9 these will be needed to be 64-bit, so bump them early, to avoid it causing any wierdness later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: factor out eop event writing code. (v2)Dave Airlie2017-06-024-65/+82
| | | | | | | | | | | | | | In prep for GFX9 refactor some of the eop event writing code out. This changes behaviour, but aligns with what radeonsi does, it does double emits on CIK/VI, whereas previously it only did this on CIK. v2: bump the size checks. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: factor out si_emit_wait_fence code.Dave Airlie2017-06-024-22/+20
| | | | | | | This code was in a few places, consolidate into one. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* intel/blorp: Handle gen6 stencil/HiZ offsets in the back-endJason Ekstrand2017-06-015-74/+41
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-013-9/+64
| | | | | | | | | Frequently, get_image_offset_sa is combined with get_intratile_offset_sa so it makes sense to have a single helper to do both. If the caller doesn't want the intratile offsets, it can simply pass NULL and ISL will assert that they are 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-013-9/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a new layout for HiZ and stencil on Sandy BridgeJason Ekstrand2017-06-012-5/+197
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Generate phys_total_el from isl_calc_phys_extentJason Ekstrand2017-06-011-68/+97
| | | | | | | | | | The only surface layout for which slice0 makes any sense is GEN4_2D. Move all of the slice0 stuff into isl_calc_phys_total_extent_el_gen4_2d and make the others trivially return the total size in surface elements. As a side-effect, array_pitch_el_rows is now returned from these helpers as well. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't check array pitch for gen4 3D texturesJason Ekstrand2017-06-011-1/+0
| | | | | | Array pitch doesn't matter in this layout. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor to use a phys_total_el extent.Jason Ekstrand2017-06-011-19/+19
| | | | | | | We've already implicitly been using a physical total size in surface elements. This just centralizes things a bit. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add an isl_assert_div helperJason Ekstrand2017-06-011-0/+7
| | | | | | | This is a fairly common operation and it's nice to be able to just call the one little function. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor isl_calc_array_pitch_el_rowsJason Ekstrand2017-06-011-47/+46
| | | | | | | | | | | Over 90% of the function only applies to ISL_DIM_LAYOUT_GEN4_2D anyway so we can just handle the other two as special cases at the top. The two "generic" cases below the switch only apply on gen9 and above and only to 3D or CCS surfaces. This implies that they only apply to surfaces with ISL_DIM_LAYOUT_GEN4_2D. Making them look generic is a lie. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Move isl_calc_array_pitch_el_rows higher upJason Ekstrand2017-06-011-117/+117
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Remove the device parameter from isl_tiling_get_infoJason Ekstrand2017-06-015-32/+17
| | | | | | | | | We were only using it for validating that we don't use Ys/Yf on gen8 and earlier. Removing it from isl_tiling_get_info lets us remove it from a bunch of other things that had no business needing a hardware generation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Rework Sandy Bridge HiZ and stencil layoutsJason Ekstrand2017-06-015-29/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandy Bridge does not technically support mipmapped depth/stencil. In order to work around this, we allocate what are effectively completely separate images for each miplevel, ensure that they are page-aligned, and manually offset to them. Prior to layered rendering, this was a simple matter of setting a large enough halign/valign. With the advent of layered rendering, however, things got more complicated. Now, things weren't as simple as just handing a surface off to the hardware. Any miplevel of a normally mipmapped surface can be considered as just an array surface given the right qpitch. However, the hardware gives us no capability to specify qpitch so this won't work. Instead, the chosen solution was to use a new "all slices at each LOD" layout which laid things out as a mipmap of arrays rather than an array of mipmaps. This way you can easily offset to any of the miplevels and each is a valid array. Unfortunately, the "all slices at each lod" concept missed one fundamental thing about SNB HiZ and stencil hardware: It doesn't just always act as if you're always working with a non-mipmapped surface, it acts as if you're always working on a non-mipmapped surface of the same size as LOD0. In other words, even though it may only write the upper-left corner of each array slice, the qpitch for the array is for a surface the size of LOD0 of the depth surface. This mistake causes us to under-allocate HiZ and stencil in some cases and also to accidentally allow different miplevels to overlap. Sadly, piglit test coverage didn't quite catch this until I started making changes to the resolve code that caused additional HiZ resolves in certain tests. This commit switches Sandy Bridge HiZ and stencil over to a new scheme that lays out the non-zero miplevels horizontally below LOD0. This way they can all have the same qpitch without interfering with each other. Technically, the miplevels still overlap, but things are spaced out enough that each page is only in the "written area" of one LOD. Cc: "17.0 17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Drop duplicate shadow variable.Kenneth Graunke2017-06-011-1/+0
| | | | | | We already initialized this at the top of the function. Trivial.
* automake: Link all libGL.so variants with -Bsymbolic.Jose Fonseca2017-06-012-0/+2
| | | | | | | | | | | | | | | | | | We were linking src/glx with -Bsymbolic, but not the classic/gallium X11 libGL.so. But it's always a good idea to build all libGL.so and all DRI drivers with -Bsymbolic, otherwise they might resolve symbols from the 3rd party application executable or shared libraries, which is _never_ what we want. In particular, this can happen when intercepting OpenGL calls with apitrace, before https://github.com/apitrace/apitrace/commit/63194b2573176ef34efce1a5c8b08e624b8dddf5 Cc: [email protected] Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer()Chad Versace2017-06-011-5/+1
| | | | | | | | | | | This function never occurs in the callchain of a GL function. It occurs only in the callchain of eglCreate*Surface and the analogous paths for GLX. Therefore, even if a thread does have a bound GL context, emitting a GL error here is wrong. A misplaced GL error, when no GL call is made, can confuse clients. Cc: [email protected] Reviewed-by: Ian Romanick <[email protected]>
* i965: Cleanup in intel_create_winsys_renderbuffer()Chad Versace2017-06-011-5/+2
| | | | | | | Combine variable declarations and assignments. Trivial cleanup. Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove bad assert on isl_formatChad Versace2017-06-011-1/+0
| | | | | | | translate_tex_format() asserted that isl_format != 0. But 0 is a valid format, ISL_FORMAT_R32G32B32A32_FLOAT. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix return type of translate_tex_format()Chad Versace2017-06-013-6/+6
| | | | | | | | | It returns an isl_format, not GLuint BRW_FORMAT. I updated every translate_tex_format() found by git-grep. No change in behavior. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix return type of brw_isl_format_for_mesa_format() [v2]Chad Versace2017-06-013-8/+10
| | | | | | | | | | | It returns an isl_format, not uint32_t BRW_FORMAT. I updated every brw_isl_format_for_mesa_format() found by git-grep. No change in behavior. v2: Rebased atop Anuj's patch, which has some of the same fixes. Reviewed-by: Jason Ekstrand <[email protected]> (v1)
* i965: Remove an extra semicolonAnuj Phogat2017-06-011-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Rename brw_format variable names to isl_formatAnuj Phogat2017-06-013-7/+9
| | | | | | | | | | This patch makes non functional changes. Renaming is just to make the code more readable. V2: update the types to "enum isl_format" Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Reject unsupported formats in glEGLImageTargetTexture2D()Chad Versace2017-06-011-0/+4
| | | | | | | | | | If the EGLImage's format is not a supported texture format according to brw_surface_formats.c, then refuse to create the miptree. This follows the precedent in glEGLImageRenderbufferStorage (implemented by intel_image_target_renderbuffer_storage), which rejects the EGLImage's format if is not renderable. Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke2017-06-016-42/+32
| | | | | | This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <[email protected]>
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