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* program: Delete dead _mesa_realloc_instructions.Matt Turner2014-12-082-21/+0
| | | | | | Dead since 2010 (commit 284ce209). Reviewed-by: Ian Romanick <[email protected]>
* swrast: Remove 'inline' from tex filter functions.Matt Turner2014-12-081-26/+26
| | | | | | | | | | Reduces .text size of mesa_dri_drivers.so (i965-only) by 62k, or 1.4%. Note that we don't remove inline from lerp_2d(), which has a comment above it saying it definitely should be inlined. Though, removing the inline keyword from it doesn't actually change the compiled code for me. Reviewed-by: Brian Paul <[email protected]>
* Don't cast the return value of malloc/reallocMatt Turner2014-12-0811-27/+17
| | | | | | | See commit 2b7a972e for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Use calloc instead of malloc/memset-0Matt Turner2014-12-081-2/+1
| | | | | | | See commit 6bda027e for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2014-12-0820-72/+39
| | | | | | | See commits 5067506e and b6109de3 for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-081-0/+29
| | | | Signed-off-by: Kristian Høgsberg <[email protected]>
* i965/skl: Emit depth stall workaround for gen9 as wellDamien Lespiau2014-12-081-1/+1
| | | | | | | | | | The docs say that we shouldn't need this workaround for gen8+, but just removing it, causes gpu hangs. We'll revisit this, but for now, just extend the workaround to gen9. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/skl: Fix GS thread count locationBen Widawsky2014-12-081-11/+18
| | | | | | | | | | SKL moves the GS threadcount to dw8 from dw7, and no longer does the divide by 2 thing. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Kristian Høgsberg <[email protected]>
* i965: Fix union usage for G++ <= 4.6.Vinson Lee2014-12-081-1/+2
| | | | | | | | | | | | This patch fixes this build error with G++ <= 4.6. CXX test_vf_float_conversions.o test_vf_float_conversions.cpp: In function ‘unsigned int f2u(float)’: test_vf_float_conversions.cpp:63:20: error: expected primary-expression before ‘.’ token Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86939 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* vc4: Interleave register allocation from regfile A and B.Eric Anholt2014-12-081-39/+38
| | | | | | | | | | | | | The register allocator prefers low-index registers from vc4_regs[] in the configuration we're using, which is good because it means we prioritize allocating the accumulators (which are faster). On the other hand, it was causing raddr conflicts because everything beyond r0-r2 ended up in regfile A until you got massive register pressure. By interleaving, we end up getting more instruction pairing from getting non-conflicting raddrs and QPU_WSes. total instructions in shared programs: 55957 -> 52719 (-5.79%) instructions in affected programs: 46855 -> 43617 (-6.91%)
* vc4: Fix decision for whether the MIN operation writes to the B regfile.Eric Anholt2014-12-081-3/+3
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* vc4: Drop dependency on r3 for color packing.Eric Anholt2014-12-081-4/+27
| | | | | | | | We can avoid it by carefully ordering the packing. This is important as a step in giving r3 to the register allocator. total instructions in shared programs: 56087 -> 55957 (-0.23%) instructions in affected programs: 18368 -> 18238 (-0.71%)
* vc4: Add support for GL 1.0 logic ops.Eric Anholt2014-12-081-2/+60
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* vc4: Add support for TGSI_OPCODE_UCMP.Eric Anholt2014-12-081-0/+12
| | | | This is being emitted now from st_glsl_to_tgsi.cpp.
* radeonsi/compute: Clamp COMPUTE_TMPRING_SIZE.WAVES to: num_cu * 32Tom Stellard2014-12-081-0/+3
| | | | This is the maximum value allowed for this field.
* winsys/radeon: Always report at least 1 compute unitTom Stellard2014-12-082-1/+3
| | | | | | | | All uses of this require that the value be at least one, so it's easier to report at least one than having to wrap all uses in MAX2(max_compute_units, 1). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Program RASTER_CONFIG for harvested GPUs v5Tom Stellard2014-12-084-6/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Harvested GPUs have some of their render backends disabled, so in order to prevent the hardware from trying to render things with these disabled backends we need to correctly program the PA_SC_RASTER_CONFIG register. v2: - Write RASTER_CONFIG for all SEs. v3: - Set GRBM_GFX_INDEX.INSTANCE_BROADCAST_WRITES bit. - Set GRBM_GFX_INFEX.SH_BROADCAST_WRITES bit when done setting PA_SC_RASTER_CONFIG. - Get num_se and num_sh_per_se from kernel. v4: - Get correct value for num_se - Remove loop for setting PA_SC_RASTER_CONFIG - Only compute raster config when a backend has been disabled. v5: Michel Dänzer - Fix computation for chips with multiple SEs https://bugs.freedesktop.org/show_bug.cgi?id=60879 CC: "10.4 10.3" <[email protected]>
* draw: (trivial): remove double semicolonRoland Scheidegger2014-12-091-1/+1
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* st/mesa: For vertex shaders, don't emit saturate when SM 3.0 is unsupportedAbdiel Janulgue2014-12-082-4/+3
| | | | | | | | | | | There is a bug in the current lowering pass implementation where we lower saturate to clamp only for vertex shaders on drivers supporting SM 3.0. The correct behavior is to actually lower to clamp only when we don't support saturate which happens on drivers that don't support SM 3.0 Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* glsl: Don't optimize min/max into saturate when EmitNoSat is setAbdiel Janulgue2014-12-082-1/+2
| | | | | | | v3: Fix multi-line comment format (Ian) Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* ir_to_mesa: Remove sat to clamp lowering passAbdiel Janulgue2014-12-081-3/+1
| | | | | | | | | | | | | | | Fixes an infinite loop in swrast where the lowering pass unpacks saturate into clamp but the opt_algebraic pass tries to do the opposite. v3 (Ian): This is a revert of commit cfa8c1cb "ir_to_mesa: lower ir_unop_saturate" on the ir_to_mesa.cpp portion. prog_execute.c can handle saturates in vertex shaders, so classic swrast shouldn't need this lowering pass. Cc: "10.4" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83463 Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* loader: Add missing EXPAT_CFLAGS to libloader.la CPPFLAGSMichael Forney2014-12-081-1/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Remove default from brw_instruction_name switch to catch missing names.Matt Turner2014-12-081-12/+5
| | | | | | | The case-range extension is available in clang and gcc at least back to 3.4.0. Signed-off-by: Chris Forbes <[email protected]>
* i965: Add missing opcode names.Matt Turner2014-12-081-0/+9
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Add opcode names for set_omask and set_sample_id.Matt Turner2014-12-081-0/+4
| | | | Reviewed-by: Chris Forbes <[email protected]>
* egl: Expose EGL_KHR_get_all_proc_addresses and its client extensionChad Versace2014-12-075-1/+23
| | | | | | | | | Mesa already implements the behavior of EGL_KHR_get_all_proc_addresses and EGL_KHR_client_get_all_proc_addresses. This patch just exposes the extension strings. See: https://www.khronos.org/registry/egl/extensions/KHR/EGL_KHR_get_all_proc_addresses.txt Signed-off-by: Chad Versace <[email protected]>
* freedreno/a2xx: silence warning about missing DEPTH32XIlia Mirkin2014-12-061-1/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: handle index_bias (i.e. base_vertex)Ilia Mirkin2014-12-061-3/+13
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add bgr565 texturing and renderingIlia Mirkin2014-12-061-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: add support for SRGB render targetsIlia Mirkin2014-12-062-9/+12
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: output RGBA16_FLOAT from fs for certain outputsIlia Mirkin2014-12-063-1/+17
| | | | | | | Fixes R11G11B10F rendering, and is required for SRGB format support. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: re-enable rgb10_a2 render targetsIlia Mirkin2014-12-061-1/+3
| | | | | | | | There were previously regressions regarding border colors, which the updated swizzle logic resolves. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix border color swizzle to match texture format descIlia Mirkin2014-12-061-4/+18
| | | | | | | | | This is a hack since it uses the texture information together with the sampler, but I don't see a better way to do it. In OpenGL, there is a 1:1 correspondence. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix alpha-blending on RGBX formatsIlia Mirkin2014-12-065-8/+55
| | | | | | | Expert debugging assistance provided by Chris Forbes. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* glcpp: Fix `can not` to `cannot` in error messageChris Forbes2014-12-072-4/+4
| | | | Signed-off-by: Chris Forbes <[email protected]>
* glcpp: Disallow undefining GL_* builtin macros.Chris Forbes2014-12-071-1/+2
| | | | | | | | Fixes the piglit test: spec/glsl-es-3.00/compiler/undef-GL_ES.vert Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/Gen6-7: Fix point sprites with PolygonMode(GL_POINT)Chris Forbes2014-12-071-0/+6
| | | | | | | | | | | | | | | | | This was an oversight in the original patch. When PolygonMode is used, then front faces, back faces, or both may be rendered as points and are affected by point sprite state. Note that SNB/IVB can't actually be fully conformant here, for a legacy context -- we don't have separate sets of pointsprite enables for front and back faces. Haswell ignores pointsprite state correctly in hardware for non-point rasterization, so can do this correctly, but it doesn't seem worth it. Signed-off-by: Chris Forbes <[email protected]> Cc: "10.4" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86764 Reviewed-by: Matt Turner <[email protected]>
* i965: Fix regs read for FS_OPCODE_INTERP_PER_SLOT_OFFSETChris Forbes2014-12-071-0/+2
| | | | | | | | | | Dead code elimination was eating the Y offset. Fixes the piglit test: spec/ARB_gpu_shader5/arb_gpu_shader5-interpolateAtOffset-nonconst Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add opcode names for FS interpolation opcodesChris Forbes2014-12-071-0/+9
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/st: don't use CMP / I2F for conditional assignments with native integersRoland Scheidegger2014-12-061-17/+45
| | | | | | | | | | | | | | | | | | | The original idea was to optimize away the condition by integrating it directly into the CMP instruction. However, with native integers this requires an extra I2F instruction. It is also fishy because the negation used didn't really honor ieee754 float comparison rules, not to mention the CMP instruction itself (being pretty much a legacy instruction) doesn't really have defined special float value behavior in any case. So, use UCMP and adjust the code trying to optimize the condition away accordingly (I have absolutely no idea if such conditions are actually hit or would be translated away somewhere else already). v2: cosmetic changes No piglit regressions on llvmpipe. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: decrease MAX_SCENES from 2 to 1Roland Scheidegger2014-12-062-1/+13
| | | | | | | | | | | | | | | | | | Multiple scenes per context are meant to be used so a new scene can be built while another one is processed in rasterization. However, quite surprisingly, this does not actually work (and according to git log, possibly never did, though maybe it did at some point further back (5 years+) but was buggy) because we always wait immediately on the rasterizer to finish the scene when contexts (and hence setup/scene) is flushed. This means when we try to get an empty scene later, any old one is already empty again. Thus using multiple scenes is just a waste of memory (not too bad, since the additional scenes are guaranteed to be empty, which means their size ought to be one data block (64kB) plus the size of some structs), without actually really doing anything. (There is also quite some code for the whole concept of multiple scenes which doesn't really do much in practice, but keep it hoping the wait-on-scene-flush can be fixed some day.) Reviewed-by: Jose Fonseca <[email protected]>
* draw: use the prim type from prim_info not emit in passthrough emitRoland Scheidegger2014-12-061-2/+2
| | | | | | | | | | | | The prim assembler may change the prim type when injecting prim ids now, which isn't reflected by what's stored in emit. This looks brittle and potentially dangerous (it is not obvious if such prim type changes are really supported by pt emit, the prim type is actually also set in prepare which would then be different). This fixes piglit primitive-id-no-gs-first-vertex.shader_test. Reviewed-by: Jose Fonseca <[email protected]>
* draw: use correct output prim for non-adjacent topologies in prim assembler.Roland Scheidegger2014-12-061-4/+4
| | | | | | | | | | | | | | | | | The decomposition done in the prim assembler will turn tri fans into tris, but this wasn't reflected in the output prim type. Meaning with a tri fan with 6 verts input, the output was a tri fan with 12 vertices instead of a tri list with 12 vertices (not as bad as it sounds, since the additional tris created would all be degenerate since they'd all have two times vertex zero but still bogus). This is because the prim assembler is used if either the input topology is something with adjacency, or if prim id needs to be injected, and for the latter case topologies without adjacency can be converted to basic ones. Unfortunately decomposition here for inserting prim ids is necessary, at least for the indexed case where we can't just insert the prim id at the right place depending on provoking vertex. Reviewed-by: Jose Fonseca <[email protected]>
* draw: kill off unneded prim assembler code for handling adjacency vertsRoland Scheidegger2014-12-062-60/+0
| | | | | | | | The default macros when the adjacency macros aren't defined will already exactly do that (that is, drop the adjacent vertices and call the non-adjacent macro). Reviewed-by: Jose Fonseca <[email protected]>
* gallium/docs: (trivial) remove STR opcode description.Roland Scheidegger2014-12-061-9/+0
| | | | | The opcode was removed alongside SFL by commit ecfe9e2ad2b5f178ef09420f8d95d49937137cd9.
* i965/fs: Perform CSE on MOV ..., VF instructions.Matt Turner2014-12-051-5/+11
| | | | | | | | | | | Safe from causing optimization loops, since we don't constant propagate VF arguments. (for this and the previous patch): total instructions in shared programs: 4289075 -> 4271932 (-0.40%) instructions in affected programs: 1616779 -> 1599636 (-1.06%) Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Try to emit LINE instructions on Gen <= 5.Matt Turner2014-12-052-0/+56
| | | | | | | | | | | | | The LINE instruction performs a multiply-add instruction (a * b + c) where b and c are scalar arguments. It reads b and c from offsets in src0 such that you can load them (it they're representable) as a vector-float immediate with a single instruction. Hurts some programs, but that'll all get better once we CSE the vector-float MOVs in the next patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77544 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add support for generating the LINE instruction.Matt Turner2014-12-051-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Set the region of LINE's src0 to <0,1,0>.Matt Turner2014-12-051-1/+10
| | | | | | | | | | | | | The PRMs say that <src0> region must be a replicated scalar (with HorzStride = VertStride = 0). but apparently that doesn't actually apply to all generations. I did notice when implementing the optimization later in this series that G45 and ILK needed this regioning. Reviewed-by: Ian Romanick <[email protected]>
* i965: Give compile stats through KHR_debug.Matt Turner2014-12-052-0/+20
| | | | Reviewed-by: Ian Romanick <[email protected]>
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